Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor

ABSTRACT

Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides an integrated circuit assembly including a semiconductive substrate comprising a plurality of field effect transistors having electrically coupled sources and electrically coupled drains comprising regions of the substrate adjacent to a surface of the substrate, and wherein the electrically coupled sources and the electrically coupled drains are collectively configured to conduct power currents in excess of one Ampere; and a package having a plurality of source contacts and a plurality of drain contacts configured to couple with the electrically coupled sources and the electrically coupled drains of the semiconductive substrate, and wherein the source contacts and the drain contacts are provided adjacent to the surface of the package.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims priority from U.S. ProvisionalApplication Serial No. 60/217,860, which was filed on Jul. 13, 2000,titled “Low Cost Ultra-Low On-Resistance High-Current Switching MOSFETfor Low Voltage Power Conversion”, naming Richard C. Eden and Bruce A.Smetana as inventors, and which is incorporated by reference herein.

PATENT RIGHTS STATEMENT

[0002] This invention was made with Government support under ContractNo. MDA-904-99-C-2644/0000 awarded by the Maryland Procurement Office ofthe National Security Agency (NSA). The Government has certain rights inthis invention.

TECHNICAL FIELD

[0003] This invention relates to power semiconductor switching devices,power converters, integrated circuit assemblies, integrated circuitry,current switching methods, methods of forming a power semiconductorswitching device, power conversion methods, power semiconductorswitching device packaging methods, and methods of forming a powertransistor.

BACKGROUND OF THE INVENTION

[0004] Computational power of digital processing circuitry is related tothe conversion of input DC power to waste heat. As digital computationalpowers increase, the associated power consumption and heat generated byprocessing devices also increase. Power supply voltages of logiccircuits have been reduced from 5 Volts to 1.2 Volts or less toalleviate excessive generation of heat and power consumption. However,reduction of power supply voltages has complicated other issues of powersupply and distribution to logic circuits. For example, electricalresistance between power supplies and logic circuits has a moresignificant impact upon efficiency as supply voltages continued to bereduced.

[0005] Some designs have provided power to PC boards at high voltages(e.g., 48 Volts) and then utilize on-board converters to convert thereceived high voltage energy to 1.2 Volt or other low voltage supplyenergy for application to logic circuits. To minimize the size of suchconverters, the stored energy requirements in the magnetics andcapacitors can be reduced by increasing the switching frequency of theconverter. However, conventional power semiconductor configurationsutilized in converters and capable of handling relatively large currentscan not typically switch efficiently at the desired switching speeds.

[0006]FIG. 1 depicts a conventional vertical geometry power MOSFETdevice having a plurality of n+ source contact regions 3 which liewithin p (body) regions 3P (typically formed as hexagonal islands),where both the p (body) regions 3P and the n+ source contact regions 3are electrically connected to the upper source contact metal 3M. Thegate conductors 2 are insulated from source contact metal 3M under whichthey lie by the insulator 3I and from the silicon substrate by the thingate insulator 2I. The gate conductors 2 cover the regions between the p(body) regions 3P, extending across the edge (surface channel) portionof the perimeter of the p (body) regions 3P to the n+ source regions 3.When the gate conductors 2 are biased more positively than the thresholdvoltage of this conventional n-channel power MOSFET, electron flowthrough these surface channel regions is induced which results inelectron flow along indicated paths 4. Electron paths 4 are formed fromthe adjacent n+ source regions 3 horizontally through the surfacechannel, vertically through the n− drain drift region 5N to the n+ drainregion 5 to the bottom drain metallization contact 6 shown in FIG. 1.This current flow path leads to values of source-drain ON resistancethat are higher than desired for efficient low voltage power conversionapplications.

[0007] The equivalent circuit of a conventional power MOSFET illustratedin FIG. 1 is depicted in FIG. 2. A p-n body diode 7 is provided from thesource 3 to the drain 6 and comprises the p body region 3P and the n-and n+ drain regions 5N and 5 shown in FIG. 1. The body diode 7 is arelatively large p-n⁻-n⁺ diode with a very large diffusion chargestorage capacity Q_(d). Accordingly, when the body diode 7 is firstreversed biased after heavy forward conduction, a large transientreverse current i_(r) flows for a substantial period of timet_(r)=Q_(d)/i_(r) which can limit usable switching frequencies.

[0008] There exists needs for improved semiconductor devices andmethodologies which overcome problems associated with conventionalarrangements.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The patent or application file contains at least one drawingexecuted in color. Copies of this patent or patent applicationpublication with color drawing(s) will be provided by the Office uponrequest and payment of necessary fees.

[0010] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0011]FIG. 1 is a cross-sectional view of a conventional vertical powerMOSFET device.

[0012]FIG. 2 is a schematic representation of the conventional powerMOSFET equivalent circuit.

[0013]FIG. 3 is schematic illustration of an exemplary synchronousrectification power converter.

[0014]FIG. 4 is an illustrative representation of exemplary componentsformed upon a monolithic semiconductor die.

[0015]FIG. 5 is a side cross-sectional view of an exemplaryhigh-current, low resistance area interconnect die package assembly.

[0016]FIG. 6 is another (top) cross-sectional view of the high-current,low resistance area interconnect die package assembly of FIG. 5.

[0017]FIG. 7 is a cross-sectional view of an alternative high-current,low resistance area interconnect die package assembly.

[0018]FIG. 8 is a detailed cross-sectional view of the package and aplanar high-current silicon switch die of FIG. 5 or FIG. 7.

[0019]FIG. 8A is another cross-sectional view of a portion of theintegrated circuit assembly of FIG. 8.

[0020]FIG. 9 is a cross-sectional view of another alternative exemplaryconfiguration of an integrated circuit assembly.

[0021]FIG. 10 is a plan view of an exemplary semiconductor die providedin a flip-chip arrangement.

[0022]FIG. 11 is a side view of an exemplary integrated circuit assemblyincluding the integrated circuit die of FIG. 10.

[0023]FIG. 12 is another side view of the integrated circuit assemblyshown in FIG. 11.

[0024]FIG. 13 is an illustrative representation depicting a plurality ofexemplary planar MOSFET devices of a power semiconductor switchingdevice.

[0025]FIG. 14 is a plan view of an exemplary arrangement of the planarMOSFET transistors of FIG. 13 fabricated within a semiconductor die.

[0026]FIG. 15 is a schematic representation of an exemplary gate driveramplifier coupled with the power semiconductor switching device.

[0027]FIG. 16 is a schematic representation of an exemplary active diodep-channel MOSFET coupled with the power semiconductor switching device.

[0028]FIG. 17 is a graphical representation depicting drain currentsversus a plurality of drain-source voltages of an exemplary powersemiconductor switching device.

[0029]FIG. 18 is another graphical representation depicting draincurrents versus additional drain-source voltages of the exemplary powersemiconductor switching device graphed in FIG. 17.

[0030]FIG. 19 is yet another graphical representation depicting draincurrents versus drain-source voltages of the exemplary powersemiconductor switching device graphed in FIG. 17 and FIG. 18.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0032] Like reference numerals represent like components withdifferences therebetween being represented by a convenient suffix, suchas “a”.

[0033] Referring to FIG. 3, a switching power converter 10 is depictedaccording to exemplary aspects of the present invention. The switchingpower converter 10 illustrated in FIG. 3 is configured as a synchronousrectification power converter. Other configurations of power converter10 are possible. The illustrated embodiment of power converter 10includes a transformer 12 comprising a primary side 14 and a secondaryside 16. Power converter 10 is configured to implement DC to DC powerconversion operations. High-current, low “on” resistance planar MOSFETpower semiconductor switching devices illustrated as reference 50provided according to aspects of the present invention are included onthe secondary side 16 of power converter 10 in the depicted embodiment.In a conventional diode rectified power converter, the switches 50 wouldbe replaced by a pair of Schottky diode rectifiers with their anodesgrounded.

[0034] Primary side 14 comprises a center-tapped primary transformerwinding 20 coupled with plural primary switching devices 22, 24 andprimary terminals 26. Switching devices 22, 24 are implementedintermediate one of primary terminals 26 and primary transformer winding20.

[0035] Secondary side 16 includes a center-tapped secondary transformerwinding 30 coupled with a plurality of secondary switches 32, 34 andsecondary terminals 36. Primary side 14 receives electricity viaterminals 26 at a first voltage and a first current in oneimplementation of power converter 10. Secondary transformer winding 30is coupled with primary transformer winding 20 and is configured toprovide electricity at a second voltage different than the first voltageand a second current different than the first current to terminals 36.For example, in the depicted exemplary embodiment, primary side 14 isconfigured to receive electricity at a first voltage greater than thevoltage provided upon secondary side 16. In addition, primary side 14receives current having a magnitude less than the magnitude of currentprovided at terminals 36.

[0036] In one exemplary application, power converter 10 is implementedto provide electricity to an associated microprocessor and/or otherprocessing device(s) in a low voltage application (e.g., 1.2 Volts, 2.5Volts) wherein utilization of diodes, for example in a dioderectification power converter, is rendered inefficient by the excessivevoltage drops across the diode rectifier switching devices. For example,power converter 10 may be utilized in a personal computer, server, workstation or other processing and logic circuitry applications, includinglow voltage, high current applications.

[0037] As shown, a controller 38 is provided coupled with primaryswitches 22, 24, secondary switches 32, 34 and secondary terminals 36.Controller 38 is configured to monitor output voltage and current viasecondary terminals 36 to control operations of power converter 10. Forexample, controller 38 controls the timing of switching operations ofprimary switches 22, 24 and secondary switches 32, 34 to implementappropriate power conversion operations and to maintain the voltage andcurrent of electricity within secondary side 16 in a desired range.

[0038] As described in detail below, secondary switches 32, 34 areconfigured to withstand power currents. Exemplary power currents includecurrents experienced within power devices which are greater than typicalsignaling currents which are usually a few tens of milliamps. Exemplarypower currents are greater than one Ampere and reach magnitudes of 100Amperes-200 Amperes or greater in exemplary configurations. Secondaryswitches 32, 34 are implemented as power semiconductor switching devices50 described herein according to additional aspects of the invention.Such devices 50 may be configured to accommodate currents approaching orexceeding 1000 Amperes in exemplary configurations.

[0039] Power semiconductor switching devices 50 comprise high currentdevices having ultra low ON resistance values (R_(on)) in exemplaryconfigurations. Utilizing power semiconductor switching devices 50described herein, R_(on) values less than 0.00015 Ohms are possible forconfigurations capable of handling 200 Amperes. Accordingly, it isfavorable to use the low voltage, high current power devices 50 assecondary switches 32, 34 having low R_(on) values for improvedefficiency.

[0040] In the depicted power converter applications, controller 38 isconfigured to sense output voltages and currents at terminals 36.Responsive to such monitoring, controller 38 applies control signals toprimary switches 22, 24 and secondary switches 32, 34 to control theoperation of the switches to maintain the voltages and currents atterminals 36 within a desired range. As illustrated, controller 38applies control signals to the gates of secondary switches 32, 34implemented as power semiconductor switching devices 50 according toexemplary aspects of the invention.

[0041] Referring to FIG. 4, an exemplary configuration of secondaryswitches 32, 34 configured as power semiconductor switching devices 50according to aspects of the present invention is illustrated. Powersemiconductor switching devices 50 individually comprise a power MOSFETtransistor which may be formed by a plurality of MOSFET transistorscoupled in parallel according to additional aspects of the invention.One common control signal is utilized to control the individual MOSFETtransistors of the power device 50. Exemplary MOSFET transistorsutilized to form an individual one of the power semiconductor switchingdevices 50 are described below as reference 174 in FIG. 13 and FIG. 14.Such transistors are implemented as planar, horizontally configuredn-channel MOSFET devices in one exemplary aspect.

[0042]FIG. 4 depicts a monolithic semiconductor die 52 containing pluralpower semiconductor switching devices 50 according to one embodiment.The semiconductor die 52 is fabricated from a monolithic semiconductivesubstrate 56 in the described exemplary embodiment. For example,semiconductor die 52 is formed from a semiconductive wafer (not shown)such as silicon, silicon carbide, gallium arsenide or other appropriatesemiconductive substrate.

[0043] In the described embodiment, portions of semiconductive substrate56 are doped with a p-type dopant providing a p-substrate or p-well. Inaddition, an n-well may also be formed within semiconductive substrate56. As described further below, n-channel MOSFET devices are formedwithin portions of substrate 56 comprising p-type portions or wells ofsubstrate 56 and p-channel MOSFET devices are formed within n-typeportions or wells of substrate 56. P-type and n-type portions ofsubstrate 56 are shown in FIG. 13 for example.

[0044] The depicted monolithic semiconductor die 52 also comprisesauxiliary circuitry 54 according to aspects of the present invention.Auxiliary circuitry 54 is circuitry apart from circuitry comprisingpower semiconductor switching devices 50. In some applications,auxiliary circuitry 54 is coupled with and favorably utilized inconjunction with power devices 50. For example, auxiliary circuitry 54comprises controller circuitry or driver circuitry to control powersemiconductor switching devices 50. In other applications, auxiliarycircuitry 54 is not coupled with and is unrelated to operations of powersemiconductor switching devices 50. In some configurations, auxiliarycircuitry 54 is implemented as application specific integrated circuitry(ASIC).

[0045] The depicted semiconductor die 52 is illustrated with respect tothe power converter 10 application of FIG. 3. Other configurations ofsemiconductor die 52 including other arrangements of power semiconductorswitching devices 50 and auxiliary circuitry 54 configured for otherapplications are possible. In the illustrated exemplary configuration,auxiliary circuitry 54 formed upon monolithic semiconductor die 52 andcomprising controller 38 and gate amplifiers 60 are configured to couplewith at least one of the electrical contacts (i.e., gate contact in thearrangement of FIG. 4) of the respective power semiconductor switchingdevices 50.

[0046] Regardless of the application of die 52 or power devices 50,aspects of the present invention provide auxiliary circuitry 54 uponmonolithic semiconductor die 52 including power semiconductor switchingdevices 50. Fabrication of power semiconductor switching devices 50using common CMOS processing methodologies according to aspects of thepresent invention or other processing techniques facilitates formationof auxiliary circuitry 54 using similar processing methodologies uponmonolithic semiconductor die 52. For example, if CMOS processes are usedto form devices 50, such CMOS processes can also be utilized to formauxiliary circuitry 54, if desired. Power semiconductor switchingdevices 50 may be fabricated simultaneously with auxiliary circuitry 54in such arrangements. The capability to provide auxiliary circuitry 54upon the semiconductor die 52 is enabled by the fabrication of powersemiconductor switching devices 50 comprising planar MOSFET devicesaccording to aspects of the present invention which may be fabricatedwithin a standard CMOS foundry ordinarily used to fabricate small-signaldigital or analog circuits.

[0047] Apart from the illustrated fabrication efficiencies of powersemiconductor switching devices 50 and auxiliary circuitry 54, there maybe other reasons to provide auxiliary circuitry 54 upon the samesemiconductor die 52 as devices 50. For example, and as describedfurther below, exemplary configurations of power semiconductor switchingdevices 50 individually comprise a plurality of MOSFETs, including forexample, thousands of parallel-coupled MOSFETs (a plurality of MOSFETswitching devices of individual power devices 50 are depicted inexemplary configurations in FIG. 13 and FIG. 14). Provision of auxiliarycircuitry 54 including control circuitry and driver circuitry upon thesame die 52 as devices 50 advantageously facilitates driving the gatecapacitances of the individual MOSFETs comprising power devices 50 andminimizes the capacitance which must be driven by external controlcircuitry such as the outputs from the converter controller 38. Furtherdetails regarding driving gate capacitances of devices 50 are describedbelow and other advantages may be gained by providing auxiliarycircuitry 54 upon monolithic substrate 56.

[0048] In particular, it may be desired to provide converter controller38 adjacent to the secondary side 16 in synchronous rectifier switchingapplications. According to embodiments described herein, auxiliarycircuitry 54 is configured as converter controller 38 provided upon die52 including power devices 50. Providing controller 38 adjacent todevices 50 is advantageous to significantly reduce parts count inproviding power converter products. Controller circuitry 38 may beimplemented using analog or digital control circuit configurations.

[0049] As mentioned above, power converter controller 38 providesrespective control signals to control the operation of secondaryswitches 32, 34 implemented as power semiconductor switching devices 50upon die 52 according to aspects of the present invention. Controller 38is also configured to apply control signals externally of semiconductordie 52. For example, controller 38 is arranged in the exemplaryconfiguration to apply control signals (Phi_(p1), Phi_(p2)) to primaryswitches 22, 24 to control switches 22, 24, generally through some typeof isolation device to enable isolation between the input side 14 andoutput side 16 grounds of power converter 10. Power controller 38 isalso coupled with output terminals 36 to sense voltages and currentswithin the secondary side 16 of power converter 10. Bond pads (notshown) are provided upon semiconductor die 52 to provide coupling of die52 with external circuitry including terminals 36 and isolation devicescoupling to primary switches 22, 24.

[0050] As discussed above, auxiliary circuitry 54 further includes gatedriver amplifier circuits 60 coupled intermediate controller 38 andrespective power semiconductor switching devices 50. Gate driveramplifier circuits 60 operate to improve power conversion operations orother operations requiring controlled switching of power semiconductordevices 50. Further details regarding an exemplary configuration ofamplifiers 60 are discussed below in FIG. 15 as reference 180.

[0051] As mentioned above and according to aspects of the invention,power semiconductor switching devices 50 may be individually implementedas a plurality of parallel-coupled MOSFETs including parallel-coupledgates, parallel-coupled sources and parallel-coupled drains. Gate driveramplifier circuits 60 are configured to provide respective controlsignals to the parallel-coupled gates of the MOSFETs of powersemiconductor switching devices 50. Depending upon the application ofpower devices 50 (e.g., application within power converter 10)significant input currents may be required to drive the MOSFET gates ofindividual power semiconductor switching devices 50. Utilization of gatedriver amplifiers 60 according to aspects of the invention facilitatesdriving these input currents and minimizes the capacitance which must bedriven by the control circuitry controlling the gates of powersemiconductor switching devices 50 providing improved switching speeds.

[0052] Further, large current spikes involved in charging anddischarging gate capacitance of power semiconductor switching devices 50comprising numerous parallel-coupled MOSFETs places demands on availablecurrent and provides a serious limitation to timing precision andpractical switching speeds. In some configurations, (e.g., someconfigurations of power semiconductor switching devices 50 comprise500,000 MOSFET devices or more arranged in parallel as described below)20 nF gate capacitances are driven. The utilization of gate driveramplifiers 60 upon semiconductor die 52 reduces the capacitance at thegate control input to the gate drive amplifiers 60 to 4.5 pF of a500,000 MOSFET device 50 which may be easily controlled directly fromdigital timing circuits such as controller 38 to precisions of a fewnanoseconds.

[0053] Alternative auxiliary circuitry 54 includes zero-currentswitching/timing circuitry to detect the absence of currents withinsecondary inductive device 30. Zero-current switching/timing circuitrymay be utilized to determine proper moments in time for controllingswitching of secondary switches 32, 34.

[0054] According to additional aspects, auxiliary circuitry 54 includesload protection circuitry configured to detect voltage overageconditions and current overage conditions. Controller 38 coupled withappropriate load protection circuitry controls operation of powersemiconductor switching devices 50 responsive thereto, including openingor closing appropriate switching devices 22, 24, 32, 34.

[0055] According to additional aspects, auxiliary circuitry 54 includesprotection circuitry configured to detect drain-source or gate-sourcevoltage overage conditions within devices 50 which could potentially bedamaging to the devices and to institute corrective action such as tomitigate the over voltage conditions. Implementation of this functionrequires coupling from the drains of the power semiconductor switchingdevices 50 through some type of internal or external voltagediscrimination elements (such as a Zener diodes or transient voltagesuppression (TVS) circuitry) back to either auxiliary inputs on therespective gate drive amplifiers 60 or to the controller 38 (FIG. 3).When the voltage discrimination element provides feedback that adangerous overvoltage condition exists at the drain of one of powerMOSFET devices 32 or 34, the protection circuitry functions to generatea gate voltage on that device such as to cause a momentary drain currentpulse capable of suppressing the overvoltage condition in the manner ofan active snubber circuit.

[0056] Exemplary configurations of zero-current switching/timingcircuitry, load protection circuitry, active snubber circuitry or otherconfigurations of auxiliary circuitry 54 are implemented as applicationspecific integrated circuitry (ASIC) as mentioned above.

[0057] The depicted exemplary configuration of device 50 withinsemiconductor die 52 is provided for discussion purposes with respect tothe exemplary power converter 10 application. Other configurations arepossible including provision of a single power semiconductor switchingdevice 50, additional power semiconductor switching devices 50 and/orother associated auxiliary circuitry 54 upon an appropriatesemiconductor die 52. Other power conversion configurations and otherapplications of power semiconductor switching devices 50 describedherein are possible. Power semiconductor switching devices 50 are usablein other low voltage, high current applications apart from exemplaryapplications described herein.

[0058] Aspects of the present invention also provide devices and methodsfor packaging of power semiconductor switching devices 50 andsemiconductor die 52 including devices 50. As set forth above, devices50 according to exemplary configurations comprise plural MOSFET devicescoupled in parallel. Examples of such MOSFETs are depicted in FIG. 13and FIG. 14 as planar, horizontally configured MOSFETs havinghigh-current power electrodes (e.g., source and drain) provided adjacenton a common surface as opposed to conventional power MOSFETs wherein thesource is provided upon an upper surface and the drain is provided uponan opposing lower surface, as illustrated in FIG. 1.

[0059] Various exemplary packaging configurations and integrated circuitassemblies according to aspects of the present invention are describedhereafter with reference to FIG. 5-FIG. 12. The illustratedconfigurations are exemplary and other packaging or assemblyarrangements are possible for power semiconductor switching devices 50,including other combinations of the various layers and electricalconnections depicted in FIG. 5-FIG. 12.

[0060] Referring to FIG. 5 and FIG. 6, a first exemplary integratedcircuit assembly 70 is shown. Integrated circuit assembly 70 includessemiconductor die 52 including one or more power semiconductor switchingdevice 50 and auxiliary circuitry 54 (if circuitry 54 is provided withindie 52). In the illustrated example, semiconductor die 52 is implementedin a flip chip configuration. Other packaging designs of semiconductordie 52 are possible.

[0061] Integrated circuit assembly 70 further includes a package 73coupled with semiconductor die 52. Package 73 comprises one or moreintermediate layer 74, a source plane 76, and a drain plane 78 (plurallayers 74, 74 a are illustrated in the exemplary package configurationof FIG. 5 and one intermediate layer is shown in the exemplaryarrangement of FIG. 3 in Appendix A).

[0062] Intermediate layer(s) 74 comprise “fineline” layer(s) in theillustrated exemplary embodiment. For example, intermediate layer(s) 74are implemented as plated copper planes (5-10 microns typical).Intermediate layer(s) 74 are capable of being patterned to horizontalfeature sizes sufficiently small as to allow area array contact to thesemiconductor die 52. Intermediate layer(s) 74 which provide electricalconduction in a horizontal direction may be referred to as horizontalinterconnect layers.

[0063] In one exemplary embodiment, drain plane 78 is implemented as aplated copper plane (0.010 inches or 250 microns typical) and plane 76is implemented as a source plane comprising copper-invar-copper (0.030inches or 750 microns typical). Other configurations of layer(s) 74 andplanes 76, 78 are possible.

[0064] For example, the drain plane 78 may be divided into two or moreportions in an exemplary alternative configuration wherein individualportions service respective portions (e.g., halves) of the area of die52 and coupled with two separate drain contact areas. In such anarrangement, a die containing two power devices 50 as illustrated inFIG. 4 could be accommodated (whereas the illustration of FIG. 5 andFIG. 6 shows only a single high-current drain contact 82, along with thesingle high-current source contact 80, suitable for a die 52 having asingle power device 50 in the depicted exemplary configuration).

[0065] In addition, the integrated circuit assembly 70 includes a singleterminal source contact 80 and a single terminal drain contact 82 in thedepicted exemplary configuration. Opposing ends of planes 76, 78 defineterminal contacts 80, 82 in the exemplary configuration. Terminalcontacts 80, 82 are configured to couple with devices external ofassembly 70 upon installation of assembly 70 into final products (e.g.,terminal contacts 80, 82 couple with a motherboard in an exemplarycomputer application).

[0066] Referring to FIG. 6, one or more gate lead replaces a drainsolder ball in the array to provide connectivity to the gate of device50. The package lead which attaches to the gate may be fabricated inlayer 74 if the gate ball is at the perimeter. FIG. 6 depicts furtherdetails of the package 73 of FIG. 5 looking downward through across-sectional line passing through intermediate layer 74 a. Die 52 andgate contact 89 fabricated using layer 74 are shown in FIG. 6 forillustrative purposes.

[0067] A plurality of electrical interconnects 84 are depicted whichcouple intermediate semiconductor die 52 and intermediate layer 74 ofpackage 73. Exemplary electrical interconnects 84 include respectivegate, source and drain solder balls 87 coupled with respective matingpads fabricated in intermediate layer 74 in one exemplary configuration.Intermediate layer 74 also provides contact to the gate (as mentionedabove) and other lower current connections to the semiconductor die 52as well as providing external package connection pads for coupling theseto a circuit board through suitable connections and can form, inconjunction with solder balls 87 and intermediate layer 74 a if desired,the electrical connection between lower current connections of die 52and their respective external package pads. Electrical interconnects 84coupled with respective source, drain, gate and other bond pads ofsemiconductor die 52 (not shown) provide connectivity of such bond padsto intermediate layer 74.

[0068] As shown in the depicted embodiment, intermediate layer 74 a isspaced from semiconductor die 52 including power semiconductor switchingdevices 50 therein. Intermediate layer 74 a provides proper coupling ofsource bond pads of semiconductor die 52 with source plane 76 andpermits coupling of drain bond pads of semiconductor die 52 with drainplane 78.

[0069] Intermediate layer 74 a is generally implemented as a sourceplane in the described embodiment. Layer 74 a is coupled with sourceplane 76 and source terminal contact 80 using a plurality of viaconductors 90 within vias 88 passing through, but insulated from, drainplane 78. Via conductors 90 provide connectivity of source plane 76 withthe proper associated source electrical interconnects 84 and sourceportions of intermediate layer 74 a.

[0070] As shown, layer 74 a includes a plurality of vias 86. Portions 77of layer 74 a within vias 86 and electrically insulated from theremainder of layer 74 a provide connectivity of respective drain bondpads of die 52 to drain plane 78. Portions of layer 74 a within vias 86provide lateral, horizontal matching of drain bond pads and respectivedrain interconnects 84 to drain plane 78 as shown illustrating layer 74a as a horizontal interconnect layer.

[0071] Electrical interconnects 84 couple source bond and drain pads ofsemiconductor die 52 with respective portions of layer 74 in thedepicted embodiment. Although not illustrated, an appropriate insulativedielectric material may be provided within vias 86, 88, intermediatesource plane 76 and drain plane 78, and intermediate source and drainportions of layer 74 a. Further, dielectric material may provided atother desired locations to provide appropriate electrical insulation,such as between planes 76 and 78, between plane 78 and layer 74 a, andbetween layers 74 and 74 a. Insulative underfill material may also beprovided beneath semiconductor die 52 to protect solder balls 87 andsemiconductor die 52.

[0072] As illustrated, FIG. 5 and FIG. 6 depict an exemplary integratedcircuitry assembly 70 comprising an area array bumped flip-chipconfiguration of die 52 mounted to a fineline augmented package 73. Thehigh density solder bump array may be provided directly upon die pads ofsemiconductor die 52 and contact a mating high density pad arraypatterned in layer 74 over layer 74 a of package 73.

[0073] Package metallization layers thick enough to handle some highsource and drain currents can not be patterned fine enough to directlymate to some chip solder bump pitches. Accordingly, in some embodiments,one or more intermediate layer (comprising fineline additivecopper/polymer interconnect layers in one embodiment as mentioned above)is implemented to provide an exemplary solution to feature size mismatchof semiconductor die 52 and package 73.

[0074] The intermediate layers are implemented to include pattern platedcopper conductor layers with patterned benzocyclobutene (BCB) sold underthe trademark CYCLOTENE available from the Dow Chemical Company, andcomprising appropriate dielectric layers in one exemplary embodiment.Other patternable dielectric materials such as polyimide could also beused as an alternative to BCB. The described exemplary intermediatelayer 74 is capable of being patterned with requisite area bump arrayfeature sizes which are thicker than on-chip metal layers (e.g.,typically 5-20 microns of copper compared to 0.4-0.8 microns of aluminumupon a CMOS die). However, such are not as thick as 10 mils (254microns) or more of copper upon main packaging layers implemented asplanes 76, 78 in the described embodiment where undivided source anddrain currents pass from the package contacts. Further details regardingsimilar or alternative configurations of package 73 are illustratedbelow and in FIG. 6A and FIG. 6B of the Appendix and described in theassociated text thereof.

[0075] Referring to FIG. 7, an alternative configuration of integratedcircuit assembly is illustrated as reference 70 a. Integrated circuitassembly 70 a may be utilized in applications having finer solder ballpitch compared to assembly 70. Integrated circuit assembly 70 a includespackage 73 a including a plurality of intermediate layers depicted asreferences 74 b, 74 c. Plural intermediate layers 74 b, 74 c comprisingfineline layers for example and configured as horizontal interconnectlayers as shown provide additional flexibility in accommodating featuresize mismatch of semiconductor die 52 and package 73 a. Additionalhorizontal interconnect layers for example implemented as additionalintermediate layers are utilized in other embodiments if desired tocouple additional source and drain bond pads of the semiconductor die 52with an associated package. Alternatively, in other configurations, thepackages are provided with no horizontal interconnect layers and sourceand drain pads of semiconductor die 52 are coupled with respectivesource and drain planes 76, 78 using appropriate via conductors 90 orother appropriate configurations.

[0076] Layers 74 b, 74 c configured as horizontal interconnect layersprovide proper connectivity of source and drain electrical interconnects84 a implemented as solder balls 87 with the respective appropriateplanes 76, 78 a. Layer 74 b provides lateral, horizontal alignment fordrain connections while layer 74 c provides lateral, horizontalalignment for source connections.

[0077] Via conductors 90 provide electrical coupling of appropriateportions of layer 74 c with source plane 76. The number of viaconductors 90 and vias 88 may be varied according to magnitude ofcurrents to be conducted. Although not shown in FIG. 7, appropriateinsulative material is provided in assembly 70 a to effectively insulatesource and drain conductors of die 52 and package 73 a.

[0078] The integrated circuit assemblies depicted herein minimizeresistance intermediate source and drain terminal contacts 80, 82. Inthe exemplary configuration of FIGS. 5 and 6, for example, a total(source+drain) package resistance of approximately 0.0001 Ohms isobserved between source and drain terminals 80, 82 in a configurationhaving a 4mm×4mm square semiconductor die 52 having a total of 256solder balls on a 250 micron pitch (in accordance with the geometryshown in FIGS. 6A and 6B of Appendix A) of a device 50 implemented as aplanar MOSFET and comprised of 500,000 MOSFET devices coupled inparallel capable of conducting currents of approximately 200 Amperes. Ifa finer solder bump pitch, such as 1600 solder balls on a 100 micronpitch were used with the same sized semiconductor die 52 using a finerpackage contact array pitch as illustrated in FIG. 7 but with the samethicknesses of intermediate layer(s) 74 and planes 76, 78 cited inconjunction with FIGS. 5 and 6, the calculated total (source+drain)package resistance is approximately 0.00008 Ohms. (As shown in FIG. 10of Appendix A, the modest 23% calculated reduction in package resistancefrom 103 microOhms to 80 microOhms by going from 256to 1600 solder ballsis accompanied by a calculated reduction in on-chip metallization [theresistance of the metallization layers on the semiconductor die 52]resistance by a factor of 3.7 from 111 microOhms to 30 microOhms).

[0079]FIG. 8 and FIG. 9 depict cross-sectional views of exemplaryassemblies for power semiconductor switching devices 50 capable ofconducting currents in excess of 200 Amperes and comprisingapproximately 500,000 planar switching MOSFET devices 174 coupled inparallel (only three n-channel devices 174 are shown in each of FIG. 8and FIG. 9, while FIG. 8A shows an end view of 8 of these n-channeldevices). The assembly 70 of FIG. 8 generally corresponds to theassembly depicted in FIG. 5 and FIG. 6. Further details of similar oralternative constructions of FIG. 8 are illustrated as FIG. 3 in theAppendix and described in the associated text therein. Further detailsof assembly 70 b of FIG. 9 are illustrated in FIG. 7 of the Appendix anddescribed in the associated text therein.

[0080] Referring to FIG. 8, details of an exemplary 5-layer ICmetallization system 100 are depicted upon a CMOS semiconductor die 52.The illustrated metallization 100 may be utilized within the assemblies70, 70 a, 70 b, 70 c and in conjunction with packages 73, 73 a, 73 b, 73c (or other assembly and package configurations) although themetallization 100 of FIG. 8 is depicted with reference to assembly 70and package 73. FIG. 8 depicts a cross-sectional view through planarMOSFET channel stripes and source and drain buss bar stripes ofmetallization 100 looking in an “X” direction. The depictedsemiconductor die 52 includes a plurality of sourcedrain regions 101 andgate regions 102 therebetween to form plural MOSFETs 174. Sourcedrainregions 101 and gate regions 102 are preferably implemented as suicideregions, comprising polysilicide for example, formed adjacent to asurface 57 of substrate 56.

[0081] Semiconductor die 52 is coupled with an exemplary package 73.Electrical interconnects 84 comprise solder balls 87 having a bump pitchof 50-250 microns utilizing normal or fine bump pitch technology inexemplary configurations providing connectivity of die 52 and package73. Further, an intermediate layer 74 a is also depicted within package73.

[0082] Metallization 100 includes plural metal layers including a firstmetal layer 110, a second metal layer 111, a third metal layer 112, afourth metal layer 113 and a fifth metal layer 114 elevationally abovesurface 57 of semiconductive substrate 56. First metal layer 110 depictssource and drain “Y” stripes having dimensions of approximately 25microns by 0.75 microns. Second metal layer 111 depicts source and drain“X” buss bars having dimensions of approximately 12 microns whileportions corresponding to gate 102 have a dimension of 2.5 microns.Third metal layer 112 depicts a source plane with drain holes havingdimensions of approximately 3 microns by 3 microns. Fourth metal layer113 depicts a drain plane having source holes having dimensions ofapproximately 3 microns by 3 microns. Fifth metal layer 114 depicts asource and drain checkerboard configuration with ball pads comprisingsource pads 116 and drain pads 118.

[0083] Further details of metallization 100 of a 200 Ampere NMOSswitching power transistor are discussed in the Appendix. Details of anexemplary metal layer 110 are discussed in the Appendix with referenceto FIG. 4B and the associated text thereof. Further details of anexemplary metal layer 111 are discussed in the Appendix with referenceto FIG. 4C and the associated text thereof. Further details of anexemplary metal layer 112 are discussed in the Appendix with referenceto FIG. 4D and FIG. 5A and the associated text thereof. Further detailsof an exemplary metal layer 113 are discussed in the Appendix withreference to FIG. 5B and the associated text thereof. Further details ofan exemplary metal layer 114 are discussed in the Appendix withreference to FIG. 5C and FIG. 5D and the associated text thereof.

[0084] The illustrated intermediate layer 74 comprising a finelineplated copper layer provides package solder bump drain and sourcecontact pads 122. In the illustrated embodiment, layer 74 is spaced fromsubstrate 56 comprising one or more power semiconductor switching device50. As described previously, this space may be filled with insulativeunderfill material.

[0085]FIG. 8A depicts an illustrative representation of first and secondmetal layers 110, 111 looking in “Y” direction while FIG. 8 and FIG. 9look in an “X” direction. Portion 117 of layer 111 comprises a drainbuss bar while portion 119 of layer 111 comprises a source buss bar.

[0086] In an alternative embodiment to that illustrated in FIGS. 5, 6, 7and 8, the intermediate layers may be fabricated on the semiconductordie 52 a instead of within the package 73. Referring to FIG. 9, analternative assembly 70 b and package 73 b are shown. Pluralintermediate layers 74 d, 74 e are depicted formed upon semiconductordie 52 a and metallization 100 including layers 110, 111, 112, 113 and114 a. Layer 74 d comprises portions electrically coupled withrespective source bond pads 116 and drain bond pads 118 of metallization114 a. In FIG. 9 the area density or pitch of electrical couplingsbetween the semiconductor die metallization 114 a and the layer 74 dneed not be limited to the solder bump density, which allows much higherarea array pad 116, 118 densities to be utilized (e.g., pad pitches of40 microns or smaller, or 10,000 or more on a 4mm×4mm semiconductor die52 a), which substantially reduces the contribution of on-chipmetallization 100 resistance to the overall chip plus package R_(on).The tight mechanical coupling in FIG. 9 between the layers 74 d, 74 eand/or their associated dielectric layers 124 a, 124 with the chipmetallization 100 over substantially the complete area of thesemiconductor die 52 a in one possible embodiment is anticipated tooffer improved robustness and potentially improved reliability over thefine-pitch solder bump approach of FIG. 7 or FIGS. 5, 6 and 8. BCBinter-layer dielectric 124 provides electrical insulation of source anddrain electrical connections. Other patternable dielectric materialssuch as polyimide could be used here in place of BCB. Layer 74 ecomprises integrated circuit source bond pads 130 and drain bond pads132 coupled with respective portions of layer 74 d. Solder balls 87 arecoupled with respective source bond pads 130 and drain bond pads 132.Solder balls 87 are additionally coupled with source solder pads 134 anddrain solder pads 136 of an external package to provide electricalconnectivity to the external package (only portions of one pair of pads130, 132 and one pair of pads 134, 136 are shown in FIG. 9). Exemplaryexternal packages include source and drain planes 76, 78 coupled withsource and drain terminal contacts 80, 82 as described previously, orthe package configuration 73 c shown in FIG. 11. Other packageconfigurations are possible which will, in their structure, incorporatepads 134, 136.

[0087] In an exemplary embodiment, fineline copper/polymer intermediatelayers 74 d, 74 e are added to a completed or semi-fabricatedsemiconductor die 52 a in a full-wafer process according to exemplaryaspects of the present invention. Because of the very low sheetresistance of the fineline copper planes 74 d and 74 e, relativelycoarse pitches may be utilized in joining the semiconductor die 52 torelatively heavy package metallization features without compromising ONresistance values (R_(on)). Such permits mating of semiconductor die 52to relatively simple and commercially available packages usingcoarse-pitch solder bump, solder patch or other joining technologies.

[0088] Referring to FIG. 10, a lower surface of another arrangement ofsemiconductor die 52 b is depicted in a flip-chip configurationcomprising a plurality of solder balls 87 arranged in an array. Asdepicted, source pads of semiconductor die 52 b and solder balls coupledtherewith and drain pads of semiconductor die 52 b and solder ballscoupled therewith are depicted in alternating columns 140, 142,respectively.

[0089] A column 144 comprises both source solder balls (S), kelvinsource and drain solder balls (K_(S), K_(D)), temperature sensing diodesolder balls (D_(P), D_(N)), gate drive amplifier solder ballconnections including ground (V_(SS)), input (G_(in)), and 2.5 Volts(V_(DD)) in one exemplary embodiment.

[0090] In an alternative embodiment, one or more columns of drain 142 orsource 140 solder balls can be assigned to V_(dd) in order to reduce theinductance and resistance of the V_(dd) connection. This can beaccommodated at the external contact level of FIG. 12 by running themetal layers contacting these V_(dd) columns out the bottom direction inFIG. 12 (in which the source and drain are on the right and left sides),or the V_(dd) contact might be extended to the right beyond the sourcecontact region.

[0091] Referring to FIG. 11, an alternative package 73 c of assembly 70c is depicted for coupling with electrical interconnects 84 comprisingsolder balls 87. Package 73 c is implemented as a vertically laminatepackage comprising a plurality of conductive layers including sourceconductive layers 150 and drain conductive layers 152 in an alternatingarrangement to couple with solder balls 87 of the flip-chipconfiguration of semiconductor die 52 b shown in FIG. 10. Layer 154corresponds to the column 144 of miscellaneous solder ball connectionsdescribed above. Package 73 c may also be utilized in conjunction withother die configurations, including the arrangements of semiconductordie 52 described above, and die 52 a having intermediate layers 74illustrated in FIG. 9. Other assembly configurations of dies andpackages are possible.

[0092] Still referring again to FIG. 11, a plurality of alternatingdielectric layers 153, 155 are provided intermediate appropriateconductive layers 150, 152, 154 as shown. In one convenient exemplaryfabrication approach, dielectric layers 153 comprise PC board layers towhich the conductive layers 150, 152 are bonded, while dielectric layers155 comprise B-stage adhesive layers which are used to bond the variousPC board layers together using, for example, the same type of laminationprocesses used to fabricate multi-layer printed circuit boards. In FIG.11 the metal layers are shown extending a substantial distance 92 abovethe extent of the circuit board and inter-board adhesive layers in thearea where contact to the solder balls is made. Typically this“pullback” region 92 from which the PCB and inter-board adhesive layersare absent can be fabricated by means of an etching or other removalprocess after the vertical laminate package is fabricated. This form ofembodiment of the invention is anticipated to offer potential benefitsin reducing stress on the solder balls due to differential thermalexpansion between the semiconductor die 52 b and the package 73 c byallowing the metal layers 150, 152 to bend in the lateral direction inFIG. 11. This beneficial mechanical compliance can be achieved in theopposite direction (that is, in the lateral direction in FIG. 12) bypatterning, for example, suitably shaped vertical slots 93 in the sourceand drain metal planes 150, 152 between the solder ball contact areas,such that the solder ball contacts are made at the top of metal “towers”which have substantial freedom to bend.

[0093] Flip-chip mounting large silicon die directly to copper or thickPCB materials may cause severe reliability problems because of the largedifferences in CTE between the materials (Si=3ppm/° C., Cu=16.6ppm/° C.,PCB=19 to 32ppm/° C.) which fatigues and breaks solder balls on thermalcycling. In a typical PCB process, the metals are backed by a PCBdielectric. In one fabrication method, the structure as shown isoriginally fabricated with the PCB dielectrics going all of the way tothe top. The PCB dielectrics are etched away or otherwise removed toprovide flexible metal towers 95.

[0094] Referring to FIG. 12, vertical laminate package 73 c isillustrated in a side view coupled with semiconductor die 52 b andelectrical interconnects 84. A source layer 150, shown in solid outline,is coupled with electrical interconnects 84 comprising source solderballs and extends to the right to provide source terminal 80 a. A drainconductive layer 152 is depicted extending in an opposite direction fromsource conductive layer 150 to provide drain terminal 82 a. Both source150 and drain 152 layers may be patterned with vertical slots 93 orother suitable compliance patterning features between solder balls toachieve lateral compliance, particularly when used in conjunction withthe pullback 92 of the PCB and inter-layer dielectrics from the ends ofthe conductor towers 95 on which solder ball contact is made. Suitableelectrically insulative underfill material, not shown in FIG. 12, may beprovided intermediate die 52 b and package 73 c.

[0095] A vertical laminate package 73 c provides ultra-low ON resistance(R_(on)) performance. As shown in FIG. 12, orientation of alternatingconductive metal layers 150, 152 in a laminate stack perpendicular to asurface of semiconductor die 52 b permits very large reductions inpackage metal resistance by extending the package structure vertically.Package 73 c depicted in FIG. 12 may be utilized by providing electricalinterconnects 84 directly upon semiconductor die 52 (e.g., flip chiparrangement) or with the utilization of additive fineline metallizationlayers 74 d, 74 e upon semiconductor die 52 a as described above in theexemplary configuration of FIG. 9.

[0096] Packaging concepts described herein provide high currentconduction while also taking advantage of low R_(on) capabilities ofdeep submicron lateral MOSFET devices realized not only at thesemiconductor device level but also at the packaged device level.Currents applied to individual power semiconductor switching devices 50are divided into a large number of parallel paths with increasingmetallization or other conductor thicknesses as the number of pathsdecreases. For example, it has been demonstrated that 250,000 individualMOSFET source and drain electrodes are coupled with 256 solder ballcontacts through the utilization of layers of metallization 100described above upon semiconductor die 52. The packaging coupled withthe semiconductor die further reduces the number of contacts from 256 inthe given example to a single source terminal contact and a single drainterminal contact comprising high current package leads.

[0097] Referring to FIG. 13, details regarding exemplary transistors 174utilized to form an exemplary power semiconductor switching device 50are illustrated. As described above, aspects of the present inventionprovide power semiconductor switching device 50 comprising a pluralityof transistors 174 coupled in parallel to conduct the large currents(1-1000 Amperes) typically experienced in power applications. The numberof transistors 174 provided to form a single device 50 is varieddepending upon the particular application of power semiconductorswitching device 50 and the magnitude of currents to be switched. Sixn-channel transistors 174 are depicted in FIG. 13 for discussionpurposes.

[0098] Semiconductor die 52 includes transistors 174 fabricated usingdeep submicron CMOS integrated circuit processes according to exemplaryaspects of the present invention. CMOS integrated circuit metallizationlayers (FIG. 8 and FIG. 9) are provided upon die 52 and are optimallypatterned for distributing high currents with low resistance and maximumcurrent handling capability as described previously in exemplaryembodiments.

[0099] The present invention provides planar high-current (i_(max)=1 to1000 Amperes) switching MOSFET devices having very low ON resistance(R_(on) =10 micro ohms to 1 milliohm typical) and relatively low gatedrive power requirements for very high efficiency in low voltage powerconversion applications. As described above, the planar device structureof transistors 174 comprising power semiconductor switching device 50provides structures wherein current flows between closely spaced (e.g.,0.1 to 0.5 microns) source and drain electrodes on the same (top)surface of the semiconductor die 52. Accordingly, aspects of the presentinvention provide devices 50 comprising high current, low R_(on)parallel-coupled MOSFETs fabricated upon a relatively smallsemiconductor die 52 using submicron to deep submicron CMOS integratedcircuit foundry processes.

[0100]FIG. 13 depicts a portion of the exemplary power semiconductorswitching device 50 comprising plural planar, horizontal geometry highcurrent switching MOSFET devices implemented in a CMOS process. Powersemiconductor switching device 50 is fabricated within a monolithicsemiconductive substrate 56, such as silicon, comprising die 52.

[0101] Portions of substrate 56 are formed to comprise p-type substratematerial 168 or p-wells in which to form n-channel devices 174. Inaddition, other portions of substrate 56 may be n-type doped to form nwells 170 to enable the formation of p-channel devices 175 if desired.An inter-layer dielectric-filled trench region 172 is typically providedfor lateral electrical isolation of n wells 170 from p-type substratematerial or p wells 168.

[0102] First metal layer 110 of metallization 100 is depicted in FIG. 13comprising source electrodes 160 and drain electrodes 162 coupled withrespective source/diffusion regions 161, 163 which correspond todiffusion regions 101. Gate electrodes 164 are provided intermediateopposing source and drain electrodes 160, 162 and insulated from thesemiconductor by a thin gate oxide to form n-channel transistors 174.

[0103] A plurality of source regions 161 and drain regions 163 areformed in p-type substrate 168 for the formation of n-channel devices174. Regions 161, 163 are doped with an n-type dopant to form n+ sourceand drain regions in the exemplary embodiment. A polysilicide layer 165may be provided intermediate electrodes 160, 162 and respectivediffusion regions 161, 163 in one embodiment to minimize resistancestherebetween. In FIG. 13, the via conductors 173 between the first levelmetal 110 and the polysilicide layer 165 are shown as part of the sourceelectrodes 160 and drain electrodes 162. Gate electrodes 164individually comprise polysilicide in one embodiment which areconfigured to couple with layers of metallization 100. As utilizedherein, the term “source” refers to structures including electricallyconductive structures proximately coupled with a source of the powertransistor and including source contact 160 and/or source region 161 forexample and the term “drain” refers to structures including electricallyconductive structures proximately coupled with a drain of the powertransistor and including drain contact 162 and/or drain region 163 forexample.

[0104] Source and drain regions 161, 163 are individually utilized toform a plurality of adjacent transistors 174 in the depicted exemplaryembodiment. For example, a given source electrode 160 and source region161 are utilized to form a transistor 174 with the drain electrode 162and drain region 163 to the right as well as being utilized incombination with the drain electrode 162 and drain region 163 to theleft of the given source electrode 160 to form another transistor device174. Accordingly, in a power device 50 configured according to thisexemplary aspect and having x number of transistors 174 coupled inparallel, x gates 164, x/2 source electrodes 160 and x/2 drainelectrodes 162 are utilized.

[0105] As depicted, semiconductive substrate 56 has a surface 57. Sourceelectrode 160, source region 161, drain electrode 162, drain region 163and gate electrode 164 are formed adjacent to surface 57 in the depictedembodiment according to the horizontal planar configuration ofCMOS-implemented transistors 174.

[0106] Source regions 161 may be connected with the p-wells in order toavoid or minimize potential problems with floating p-wells at excessivedV/dt occurrences. Other configurations of transistors 174 are possible.

[0107] Power semiconductor switching devices 50 individually comprise aplurality of planar horizontally configured submicron MOSFET transistors174 individually including a source electrode 160, drain electrode 162,and gate electrode 164. According to one exemplary embodiment, a singlepower semiconductor switching device 50 comprises 500,000 or moretransistors 174 coupled in parallel to provide a low voltage, highcurrent power device 50. In such an embodiment, source electrodes 160 oftransistors 174 are coupled in parallel, drain electrodes 162 arecoupled in parallel and gate electrodes 164 are coupled in parallel.Provision of parallel coupled n-channel devices 174 enables power device50 to conduct currents in excess of one Ampere. An exemplary device 50comprising 500,000 transistors 174 coupled in parallel on a 4 mm×4 mmsilicon die 52 enables conduction of currents up to approximately 200Amperes.

[0108] The number of transistors 174 implemented within a given device50 varies depending upon the application or implementation of device 50,as well as the width selected for the individual transistors to beparalleled (taken as 25 microns for the examples cited herein). Thecurrent handling capability, die size and R_(on) values for a device 50vary corresponding to the numbers of transistors 174 utilized. Forexample, a very small semiconductor die 52 having an approximate area of0.16 mm² provides approximately 5,000 parallel-coupled transistors 174which conduct currents of approximately 2 Amperes with an R_(on) ofapproximately 0.01-0.02 Ohms (inclusive of n-channel MOSFET ONresistance and on-chip metallization resistance, but not includingpackage resistance), while a die of 1.6 mm² provides approximately50,000 parallel-coupled transistors 174 enabling conduction of currentsof approximately 20 Amperes with an R_(on) of approximately 0.001-0.002Ohms, and a die area of 16 mm² provides approximately 500,000parallel-coupled transistors 174 which enables conduction of currents ofapproximate 200 Amperes with an R_(on) of approximately 0.0001-0.0002Ohms, and a die area of 80 mm² provides approximately 2,500,000parallel-coupled transistors 174 which conduct currents of approximately1000 Amperes with an R_(on) of approximately 0.00004-0.00008 Ohms.Further details of FIG. 13 are discussed in the Appendix with referenceto FIG. 1B and the associated text thereof.

[0109]FIG. 14 depicts an elevational plan view of a region of anexemplary semiconductor die 50 illustrating n-channel transistors 174forming power semiconductor switching device 50. The illustrated regionincludes a plurality of rows 176 individually including a plurality oftransistors 174. The number of rows 176 is varied and the number oftransistors 174 within a row 176 is varied depending upon theimplementation of device 50, the magnitude of currents to be conductedand desired R_(on) values. In one exemplary implementation of powerdevice 50 having a row 176 height of 25 microns (corresponding to thewidth of each of the individual transistors), 500,000 transistors 174,250,000 source regions 161, 250,000 drain regions 163 and 500,000 gates164 are provided in a 4 mm×4 mm (16 mm²) die size as implemented in anominal 0.24 micron feature size CMOS process. The R_(on) and number oftransistors in a given die size are typically closely tied to the ICfeature size. The number of transistors also depends on the selection ofrow height.

[0110]FIG. 14 depicts transistors 174 upon surface 57 of substrate 56(FIG. 13). Source regions 161, drain regions 163 and gates 164 includepolysilicide 165 (FIG. 13). A plurality of via conductors 173 areprovided upon respective source regions 161 and drain regions 163 andvia conductors 177 are provided upon gates 164 to provide verticalconnectivity to first metal layer 110 elevationally over substrate 56 asshown in FIG. 8 and FIG. 9, for example.

[0111] Individual rows 176 provide transistors 174 individually having achannel length of approximately 25 microns. In an exemplary nominal 0.24micron feature size commercial CMOS process using aluminummetallization, individual rows 176 provide W=250 microns of NFET widthin a 10 micron horizontal distance. Polysilicide 165 (FIG. 13)comprising source regions 161 and drain regions 163 provides ohmiccontacts of 4 Ohms/Sq. Via conductors 173, 177 provide 7.5. Ohms/cut toreduce current path resistance. Polysilicide comprising gate 164provides an ohmic contact of 7 Ohms/Sq. In the described exemplaryconfiguration, metal layers 110, 111, 112 and 113 (FIG. 8 or FIG. 9)have sheet resistances of 0.08 Ohms/Sq., while the top metal layer 114has a sheet resistance of 0.04 Ohms/Sq., with a via resistance of 5Ohms/cut between all metal layers. Other constructions of transistors174 and connections to transistors 174 are possible. In particular, theR_(on) and current carrying capacity of the devices could be improved ifa CMOS or other IC process using copper, rather than aluminum,metallization is used for fabrication. Further details regardingsubstantially similar or alternative constructions of FIG. 14 arediscussed in the Appendix with reference to FIG. 4A and the associatedtext thereof.

[0112] Referring to FIG. 15, power semiconductor switching device 50 isillustrated as a power transistor having source terminal contact 80,drain terminal contact 82 and a gate electrode 83. Power semiconductorswitching device 50 is coupled with an exemplary gate driver amplifier180 utilized to drive the gate electrode of power device 50 coupled witha plurality of parallel-coupled gates of transistors 174. Amplifier 180is one exemplary configuration of amplifiers 60 described above. Morespecifically, gate driver amplifier 180 may be implemented as auxiliarycircuitry 54 upon semiconductor die 52 in one configuration as describedabove and corresponding to amplifiers 60 of FIG. 4.

[0113] The illustrated exemplary gate driver amplifier 180 includes afirst stage 182 and a second stage 184. First driver stage 182 includesa p-channel device 186 wherein W_(d1p)=2 mm and an n-channel device 188wherein W_(d1n)=1 mm. Second driver stage 184 includes a p-channeldevice 190 wherein W_(d2p)=100 mm and an n-channel device 192 havingW_(d2n)=50 mm.

[0114] An input node 193 is configured to receive control signals froman appropriate source, such as power converter controller 38, in oneembodiment. In the configuration wherein power semiconductor switchingdevice 50 comprises 540,000 n-channel devices an input capacitance atnode 193 is approximately 4.5 pF. At a node 194 intermediate first stage182 and second stage 184, a capacitance of approximately 225 pF ispresent. Node 195 of second driver stage 184 is coupled with gateterminal 83 of power semiconductor switching device 50 where acapacitance of approximately 20 nF is present.

[0115] Power semiconductor switching device 50 comprising 540,000transistors 174 coupled in parallel provides W_(n)=13,500 mm. Powersemiconductor switching device 50 conducts currents of 200 Amperes inthe depicted embodiment with a 5 mm×5 mm die size and can accommodatecurrents of 1000 Amperes if the switching device, amplifier and die sizeare scaled up to a 10 mm×10 mm die size. In the exemplary 0.24micronCMOS process, V_(DD) is approximately 2.5 Volts and V_(SS) ground in theillustrated arrangement, assuming the source terminal 80 to be nearground potential as used in FIGS. 3 and 4.

[0116] According to certain aspects of the invention, a bypass capacitor200 is coupled with the source of power semiconductor switching device50 and V_(DD). Bypass capacitor 200 is greater than or equal to 20 nF inthe depicted exemplary embodiment. Bypass capacitor 200 is configured toprovide adequate pulse current to charge a capacitance of the gates ofparalleled coupled transistors 174 of power semiconductor switchingdevice 50 responsive to control signals received via input 193.

[0117] In one embodiment of this invention, bypass capacitor 200 isimplemented monolithically on a CMOS chip using gate to channelcapacitance of a large number of large gatelength (e.g., L_(g)=10microns) n-channel MOSFETs in parallel with their common gate electrodeconnected to V_(dd) 184 and their source and drain electrodes connectedto the output source electrode 80.

[0118] In addition, connecting the source of n-channel device 192 withthe source of power semiconductor switching device 50 obviates a needfor a separate body diode inasmuch as power semiconductor switchingdevice 50 turns on if the drain 82 thereof becomes substantially morenegative than the source 80. Alternative body diode configurations aredescribed below. Further details of the exemplary circuitry of FIG. 15are described below with reference to FIG. 8 of the Appendix and theassociated text of the Appendix.

[0119] Referring to FIG. 16, power semiconductor switching device 50 isdepicted coupled with an active diode connected p-channel MOSFET 202.The drain 206 and gate 208 of the p-channel MOSFET 202 are connected asillustrated to provide a body diode circuit turning on when the drain206 becomes more negative than the source 204 by an amount greater thanthe threshold voltage V_(t) of transistor 202. As opposed to aconventional prior art vertical geometry power MOSFET of FIGS. 1 and 2in which the diffusion stored charge, Q_(d) in the body diode 7 can bevery large, and a serious limitation to switching speed and efficiency,the stored charge in exemplary devices 50 according to aspects of thisinvention (e.g., FIG. 16) is very small, principally that stored in thegate capacitance of the switching device 50.

[0120] If the gate 83 of power semiconductor switching device 50 isconstrained to go no more negative than the source 80, it inherentlyacts as a body diode and transistor 202 may be omitted if desired. As aconsequence, with the gate driver amplifier configuration of FIG. 15, inwhich the voltage at the gate terminal 83 of the switching device 50 isconstrained to go no more negative than that at its source 80, thisn-channel MOSFET active body diode is obtained automatically in theswitching device 50. For this exemplary device 50, the stored chargethat is removed in switching from a 200 Ampere active body diode current(typically at V_(ds)=−0.75 Volts) to V_(ds)=0 Volts is less than about15 nanoCouloumbs, which is far less than for conventional prior artvertical geometry power MOSFET devices (FIGS. 1 and 2). Alternatively,device 202 is implemented as an n-channel MOSFET in another embodimentwith the gate 208 thereof connected to the source 204 thereof to alsoserve as an active body diode circuit. Body diode circuitimplementations are coupled with the source 80 and drain 82 of the powersemiconductor switching device 50 in the depicted embodiment to conductfree wheeling currents which may be present within power converter 10during switching operations or present during operations in otherapplications. Further details of FIG. 16 are discussed in the Appendixwith reference to FIG. 2B and the associated text thereof. Other circuitconfigurations to conduct free wheeling currents are possible.

[0121] Aspects of the present invention provide a plurality of planar,horizontally configured MOSFET devices 174 configured to form a powersemiconductor switching device 50 having contacts including ahigh-current source terminal contact 80 and high-current drain terminalcontact 82 on a common surface 57 of a semiconductor die 52. Additionalaspects enable electrical connectivity of terminal contacts 80, 82 todevices provided upon the common surface 57 of semiconductor die 52using convenient package configurations. Other aspects of the inventionare contemplated and provided, some of which are described above and inthe attached Appendix, the contents of which are incorporated herein byreference.

[0122] For comparison purposes, power semiconductor switching devices 50configured according to exemplary aspects of the present inventionincluding an exemplary 0.24 micron feature size (0.19 micron L_(eff)))CMOS process are discussed below with respect to a conventional verticalpower MOSFET (FIG. 1) having equivalent ON resistance R_(on) values.Power semiconductor switching devices 50 of some aspects of theinvention have twenty four times smaller die area than conventionalvertical arrangements, approximately thirty times less gate capacitance,478 times lower gate drive power at a given frequency(P_(gate)/f_(clock)), and the exemplary semiconductor die configurationsdescribed herein may be fabricated by a standard CMOS integrated circuitfoundry if desired as opposed to processes to form vertical conventionalconfigurations.

[0123]FIG. 17-FIG. 19 depict respective graphical representations 240,250, 260 of electrical performance characteristics of an exemplary powersemiconductor switching device 50 which embodies aspects of the presentinvention. The graphed power device 50 comprises a 200 Ampere powerdevice 50 having 514,000 n-channel MOSFETs 174 providing W=12,850,000microns and L_(eff)=0.19 microns.

[0124]FIG. 17 depicts drain currents of the exemplary power device 50for values of V_(GS)=0.5-2.5 Volts in 0.5 Volt increments over itsnominal 0 to 2.5 Volt drain voltage range and over an I_(d)=0 to 8000Ampere range high enough to include its I_(dss)=7700 Ampere saturateddrain current at V_(gs)=+2.5 Volt value. Note that sustained operationat high values of drain currents (e.g., above 200 Amperes) may not bepossible because of metal migration reliability issues, and operation atcombinations of high drain voltages and drain currents should be kept ofshort duration because of thermal power dissipation and energyabsorption limitations.

[0125]FIG. 18 depicts drain currents of the exemplary power device 50for values of V_(GS)=0.45-0.7 Volts in 0.05 Volt increments over itsnominal 0 to 2.5 Volt drain voltage range and over the I_(d)=0 to 200Ampere range within which sustained operation is specified (subject topower dissipation and energy absorption limitations).

[0126]FIG. 19 depicts drain currents for a V_(GS) value of 2.5 Voltsover the I_(d)=0 to 200 Ampere range within which sustained operation isspecified and over the 0 to 0.05 Volt drain voltage range within whichsustained operation is normally seen for a device of this size when thedevice is ON (Vgs=+2.5 Volts) in the exemplary power conversionapplications of the type illustrated in FIGS. 3 and 4.

[0127] Reference 262 of FIG. 19 depicts, at any given drain currentwithin transistors 174 of an exemplary power device 50, the voltagedrop, V_(ds), measured from the transistor drain contact 163 to sourcecontact 161 in FIG. 13 assuming approximately equal sharing of totalcurrent I_(d) between all transistors 174. The slope of this line is theR_(on) of the transistor devices 174 themselves, exclusive of on-chip orpackage metal resistance.

[0128] Reference 264 depicts, at any given drain current, the voltagedrop, V_(ds), measured from the chip drain pads 118 to source pads 116in FIG. 8, assuming approximately equal sharing of total current I_(d)between all source 116 and drain 117 pads. The slope of this line is theR_(on) of the transistor devices 174 themselves plus that of the on-chipmetallization 100 for the case of a 4 mm×4 mm die having a total of 256solder balls, exclusive of package metal resistance.

[0129] Reference 266 depicts at any given drain current, the voltagedrop, V_(ds), measured from the package drain contact 82 to packagesource contact 80 in FIGS. 5 and 6, assuming uniform distribution ofcurrent across the width of these package contacts 80, 82, for the caseof a 4 mm×4 mm die having a total of 256 solder balls and the packagemetallization thicknesses discussed in conjunction with FIGS. 5 and 6,and in Appendix A. The slope of this line is the total R_(on) of thepackaged transistor inclusive of the transistor devices 174 themselvesplus that of the on-chip metallization 100 and the package metalresistance.

[0130] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

APPENDIX A Low Cost Ultra-Low On-Resistance High-Current SwitchingMOSFET for Low Voltage Power Conversion Richard C. Eden SUMMARY OF THEINVENTION

[0131] The use of diodes for output current rectification in low outputvoltage switching power converters or power supplies is precluded by thesevere loss in efficiency due to the forward voltage drop of diodesbecoming comparable to the desired output voltage, V_(out), of theconverter. The use of MOSFETs or other similar high-current switchingdevices in a synchronous rectifier approach can overcome this efficiencyproblem if the “on” resistance, R_(on), of the current switching MOSFETsis sufficiently low to make the I_(out)R_(on) voltage drop of across theswitches much lower than V_(out). This can be achieved with conventionalMOS power FETs by making the FET periphery (total channel width, W) verylarge, either by making one very large device, or by connecting manysmaller devices in parallel. In either approach, to achieve very lowR_(on) values, the device cost becomes quite large due to the large sizeof a single die, or the large number of paralleled devices. Also, thetotal gate capacitance of all of these devices becomes very large, whichlimits the attainable switching speed and causes significant losses inconverter efficiency due to the large ac gate drive power requirements.

[0132] Aspects of the present invention take advantage of the fact thatin a switching converter application, the breakdown voltage, V_(b),required for the synchronous rectifier switching devices is, for anoutput voltage of V_(out), only about V_(b)=2V_(out). For example, foran output voltage of V_(out)=1.2V, a breakdown voltage of aboutV_(b)=2V_(out)=2.4V is adequate for the synchronous rectifier MOSFETswitches. In aspects of this invention, this low breakdown voltagerequirement is exploited to enable implementation of the synchronousrectifier switching MOSFETs with an inexpensive commercialdeep-submicron CMOS integrated circuit foundry process (instead of thespecial higher voltage process normally used for fabricating powerMOSFET devices). For a given R_(on), compared to standard MOS power FETprocesses, the use of a very short channel length (e.g., L_(eff)=0.19μm)/very small feature size (e.g., 2λ=0.24 μm) commercial IC process forfabricating the current switches dramatically reduces the size and costof the devices, and also greatly reduces the gate capacitance andincreases switching speeds for higher efficiency and smaller convertersize.

[0133] The dramatic size/cost reduction comes through the combinedeffect of a reduction in the MOSFET periphery, W, required to achieve agiven value of R_(on) (because of the very small L_(eff)), with the factthat the very small feature size allows packing a given MOSFET peripheryinto a much smaller chip area. For example, at the silicon device level,an extremely low “on” resistance of less than R_(on)=75 μΩ can beachieved for a 200 amp switching MOSFET with a total L_(eff)=0.19 μm FETperiphery of less than W=13.5 meters, and with a 2λ=0.24 μm featuresize, this W=13.5 meter MOSFET can be packed into a chip only 4mm×4mm indimensions. At an estimated foundry CMOS foundry wafer cost of $1500 per8″ (200 mm) wafer, the unpackaged die cost for such a 200 amp switchingMOSFET chip should be less than $1.00. This deep-submicron approachgives not only a much smaller solution to achieving an extremely lowR_(on) 200 amp current switching MOSFET, but promises to be 10× to 100×cheaper than implementations using standard power MOSFET processes. Inaddition, because of the reduced FET periphery and very short(L_(g)=0.24 μm drawn) gate length, the gate capacitance is far lower,and the switching speed much higher than in the power MOSFETimplementation, and the ac gate drive power at a given switchingfrequency can be reduced by nearly a factor of 500 over conventionalvertical geometry power MOSFETs.

[0134] Also important to some aspects of this invention is the solutionof the problem of getting such large (e.g., 200 amp) currents into andout of the small (e.g., 4 mm×4 mm) FET chip without encountering metalmigration reliability problems or unduly compromising R_(on) from theon-chip metal resistance or package resistance. Conventional powerMOSFETs take the source and drain currents out of opposite faces of thedie (e.g., all of the area devoted to source contacts, plus the gateleads, are on the top surface of the die, while the drain contact is theentire back surface of the die. Having the high-current source and draincontacts on opposing surfaces of the die makes the diepackaging/interconnect quite easy. A disadvantage of using a CMOSintegrated circuit process instead of a power MOSFET process is theunavailability of this backside drain contact configuration. The MOSFETgeometries in commercial CMOS IC processes are purely lateral; that is asource-gate-drain electrode structure on the top surface of thesemiconductor die. Hence, in order to implement aspects of thisinvention and use a commercial deep-submicron CMOS process to make thelow R_(on) current switching MOSFETs, we have to be able to get both thehigh current source and drain contacts (plus one or more gate leads) offof the same (top) surface of the die. The key to the solution of thishigh-current chip packaging/interconnect interface problem is to coverat least substantially the entire area of the die with a fine pitch areaarray of solder bump contacts which flip-chip mate with a matching arrayon a very low resistance multi-layer metal package. It is desirable thatthe pitch of these solder bump contacts be as low as possible tominimize the metal resistance. While a standard commercial practice areaarray bump pitch of 250 μm is adequate to give a total (i.e., siliconFET+on-chip metal+solder bump+package metal) resistance of the order of285 μΩ, with a smaller, 100 μm bump pitch (which is also commerciallyavailable), the total R_(on) can be reduced to less than 180 μΩ for theMOSFET chip example cited above. This very low resistance is a result ofthe sharing of the source and drain current by a large number of solderbump contacts (e.g., 126 bumps each for the 250 μm pitch and about 800bumps each for the 100 μm pitch, which accounts for its better R_(on)performance).

[0135] In summary and in accordance with exemplary aspects of theinvention, the use of a commercial deep-submicron CMOS integratedcircuit process in conjunction with an area array solder bump flip-chippackaging approach allows the achievement of high-current (e.g. 200amp), very low on resistance low voltage MOSFETs having much lower costand much lower gate capacitance, not to mention much smaller size, thandevices implemented using conventional power MOSFET processes.

BACKGROUND OF INVENTION

[0136] A key focus of modern digital electronics is to achieve extremelyhigh computational densities; that is, to cram as much computationalthroughput as possible into a limited space. The relationship betweensomething as seemingly tenuous or intangible as computational power anda simple concrete physical quantity like dc power input or waste heatgenerated may not be obvious. In fact, computational throughput(“power”) is, as a matter of physics, tied to the conversion of dc inputsupply power to heat. Moreover, in the most efficient forms of logiccircuitry, the level power consumption/heat generation is essentiallyproportional to the computational throughput, albeit the exact value ofthe constant of proportionality is dependent on details of theintegrated circuit (IC) technology used to implement the computer.Specifically, it can be shown that for CMOS logic (in which the dynamicpower dissipation dominates), a chip with N_(g) gates, each driving anaverage load capacitance, C_(gl), operating at a supply voltage, V_(dd),and at a clock frequency, F_(c), with a fraction, f_(d), of those gateswitching on each clock cycle, the chip power, P_(d), will be given by

P _(d)=½f _(d) N _(g) C _(gl) V _(dd) ² F _(c)   Eq. 1

[0137] Since a reasonable measure of computational activity is thenumber of such logic gates that have switched, the measure ofcomputational throughput (rate) is simply the number of such logic gatesswitching per unit time, f_(d)N_(g)F_(c), or

Computing Rate ∝f _(d) N _(g) F _(c) =P _(d)/[½C _(gl) V _(dd) ² ]∝P_(d)   Eq. 2

[0138] which shows the (technology dependent) proportionality betweencomputational throughput and the power consumed (dissipated). What thismeans is that the quest for high computational density forces designersto cope with both high power supply densities, as well as the ability tohandle high reject heat densities.

[0139] Advances in integrated circuit technologies, principally throughthe reduction in lithographic feature sizes and FET gate lengths intothe deep submicron region, have made it possible to put millions oflogic gates on a single monolithic IC chip, as well as to increase clockrates, F_(c), into the 500 MHz to 1 GHz region. This means, from Eq. 2,that since both n_(g) and F_(c) have been increased, remarkably highcomputational throughputs can be achieved even on a single chipmicroprocessor. While feature size reductions also serve to reduce CMOSFET gate capacitances (C_(gs) and C_(gd)), much of the gate loadingcapacitance, C_(gl) in Eqs. 1 and 2, is due to interconnect wirecapacitance, which is principally a function of wire length, and hencedoes not scale strongly with feature size. This means that if the logicpower supply voltage were held constant, the chip dissipations wouldbecome astronomical (e.g., many kilowatts) for these very dense, highthroughput chips. This problem has been recognized by the semiconductorindustry, and as a consequence the power supply voltages have beengradually reduced over the last decade from their original V_(dd)=5.0 Vlevel down to V_(dd)=1.2 V for the latest 2λ=0.24 μm feature size,L_(eff) =0.19 μm gatelength CMOS logic.

[0140] While this reduction on V_(dd) has helped keep chip powerdissipations to a manageable level (typically under 100 W to 200 W perchip), which helps the thermal management problem, in fact it has insome ways made the power supply/distribution problem even moredifficult. The problem is that while the chip power requirements havebeen maintained at tolerable levels, the power supply currentrequirements have increased sharply, while at the same time thetolerance for IR voltage drops in the power distribution conductors hasbecome more severe. For example, consider a logic power (in one or morechips) requirement of P_(d)=240 W. In the “old days” of V_(dd)=5 Vlogic, from P_(d)=V_(dd)I_(s), the required supply current would beI_(s)=240/5=48 amps, and for a 10% dc noise margin allowableV_(ndc)=I_(s)R_(s)=0.5 V drop, the allowable wiring resistance betweenthe power supply and the logic is R_(s)=0.5/48=10.4 mΩ. With the reducedV_(dd)=1.2 V logic, the required supply current would beI_(s)=240/1.2=200 amps, and for a 10% dc noise margin allowableV_(ndc)=I_(s)R_(s)=120 mV drop, the allowable power distributionresistance from supply to logic is only R_(s)=0.12/200=600 μΩ. It isprobably obvious that it is very difficult to achieve such low powerdistribution resistances. While it is correct that the use of anon-board regulator near the logic chips could make it much easier tomeet the dc noise margin requirements of the logic, note that atI_(s)=200 amps, even a R_(s)=1.0 mΩ wiring resistance (including theregulator resistance) between the power supply and the logic chips willreduce the power efficiency by over 14%, so sub-millivolt resistancesare indeed required. Conventional circuit board connectors, etc., arenot capable of handling 200 amp currents with sub-millivolt resistances,so another approach is needed.

[0141] The most attractive approach to solving this problem is todistribute the power to the boards at a high voltage (e.g., V_(in)=48volts), using very efficient on-board power converters to convert thisto the V_(dd)=1.2 volt logic supply level. In order to insure that theon-board power conversion does not unacceptably compromise the overalldensity of the electronics, it is desirable to make the on-board powerconverter as small as possible. In a switching converter, the storedenergy requirements in the magnetics (e.g., transformers and inductors)and in bypass or filter capacitors can be reduced by increasing theswitching frequency, f_(s), of the converter. This is difficult,however, because of the limited switching speeds of most semiconductordevices capable of handling large currents. Addressing this deficiencyis one focus of aspects of this invention; that is to provide low costMOSFET switches capable of handling high currents at high switchingspeeds.

[0142] While the use of on-board power conversion to efficiently supplylow voltage logic requirements in high-performance systems is extremelyattractive, there is an inherent difficulty with achieving highefficiency, very small low voltage power converters. The ordinary methodof building a switching converter involves a transformer to convert downto low voltage ac, with diodes to rectify this to dc. If the forwardvoltage drop of these rectifier diodes is V_(f) and the output voltageis V_(out), then the voltage loss in the diodes alone will limit theattainable rectifier efficiency, η_(r), to a value less than

η_(r) ≦V _(out)/(V _(f) +V _(out))   Eq. 3

[0143] Typical Schottky diode forward voltage drops are of the order ofV_(f)=0.55 V or more. In the “old days” of 5 volt supplies, this diodeefficiency limit, about η_(r)=90%, was quite acceptable. With the newlow supply voltages, this is no longer the case, as Eq. 3, withV_(f)=0.55 V, gives a limiting efficiency of about η_(r)=69% atV_(out)=1.2 volts, or about η_(r)=62% at V_(out)=0.9 volts. These areunacceptably low values of conversion efficiency.

[0144] The solution to this problem is to employ MOSFET current switchesin place of the diodes (this approach is called synchronousrectification). If the MOSFET “on” resistance, R_(on), is sufficientlylow, this rectification efficiency loss may be kept very low.Unfortunately, using commercial devices fabricated with the standardvertical “power MOSFET” device structure, to get a low enough R_(on)value, it is often necessary to parallel large numbers of power MOSFETdevices in each of the two current switching positions in the circuit.Also, the enormous gate capacitance of all of these power MOSFETs makesgate drive very difficult and causes significant efficiency loss due to½C_(gs) ΔV_(g) ² F_(c) gate drive power. This, plus the limitedswitching speeds of the standard power MOSFET devices, effectivelylimits the usable switching frequency of the converters. Since the sizeof the magnetics (and capacitors) goes inversely with the frequency,this makes it very difficult to miniaturize the converters for on-boarduse (of course, having large numbers of power MOSFETs gives a sizeproblem itself).

DESCRIPTION OF THE EXEMPLARY ASPECTS OF THE INVENTION

[0145] Aspects of the invention achieve extremely low R_(on) values andextremely low gate capacitances/high switching speeds in a MOSFETcurrent switching device, including a packaging approach enabling it tobe used in circuits. Some concepts of the invention use a completelydifferent device structure from the vertical geometry of power MOSFETs;in fact, to make current switching MOSFETs in a horizontal (planar)geometry using the same 0.25 μm to 0.18 μm CMOS IC processes that areused to fabricate the high-speed logic chips themselves. While thetransistors in these deep-submicron short-channel CMOS processes haveonly about 2.5-3 volt breakdown voltages, for a synchronous rectifierhaving V_(out)=1.2 volt, a V_(br)=2.4 volt breakdown voltage is adequatefor the transistors. With this approach, in a chip only 4 mm×4 mm insize, it is possible to switch currents of 200 amperes and to achieve avalue of R_(on) superior to that of the parallel combination of dozensof power MOSFETs, and at a very small fraction of the gate capacitance.This makes it possible to reduce the ac gate drive power required toswitch to a given R_(on) value at a given switching frequency by nearlya factor of 500 over conventional vertical power MOSFETs.

[0146] Other aspects of the invention provide a packaging approachcapable of getting 200 amperes into and out of such a small chip withoutsubstantially degrading the R_(on) value. Whereas the vertical geometry,of a conventional power MOSFET has the source lead on the top surface ofthe die and the drain lead on the bottom, in the horizontal or planarMOSFET structure, the source and drain leads (as well as the gateconnection) are on the top surface of the device. On-chip metallizationlayers on semiconductor die generally have substantial sheet resistances(e.g., 40-80 mΩ/square) and limited current carrying capacity. Thismakes combining the distributed MOSFET currents from the myriad ofelemental MOSFET devices spread over the area of the chip into singlesource and drain MOSFET chip contacts on the top surface of the diewithout unacceptably degrading both R_(on) and the current switchingcapacity of the chip. In aspects of this invention, a solution to thispackaging/interconnection problem for current switching MOSFETsfabricated in the horizontal or planar structure is to utilize an areaarray of a large number (many hundreds to thousands) of chip source anddrain contact pads (plus gate pads) covering the top surface of the die.With the very large source and drain currents divided into a largenumber of parallel paths, the aggregate current carrying capacity can bevery large and the metal contribution to the chip on resistance can besmall. The area pad array may be flip-chip mated to a mirror-image areapad array in a very low resistance package. A multi-layer packageapproach utilizing thick copper interconnect layers has been designed tomeet the requirements of contacting such an area array planarcurrent-switching MOSFET chip with capability for handling 200 amperecurrents with package contribution to total on resistance of less than100 μΩ.

[0147] The achievement of an inexpensive, ultra-low on resistance planarcurrent switching MOSFET is anticipated to have a wide range ofapplications in addition to efficient low-voltage on-board powerconversion. Very low R_(on) MOSFETs could have application in a widevariety of low-voltage high-current applications, ranging from linearapplications such as high-current regulators and drivers to switchingapplications such as efficient high-density power supplies andconverters, including solar cell power conversion, and switch-modedrivers for motors and actuators.

Comparison of Device Structure of Aspects of the Invention toConventional Power MOSFET

[0148] The dramatic difference between the horizontal or planar geometrycurrent switching MOSFET structure of aspects of this invention and thevertical geometry of a conventional power MOSFET is illustrated in FIG.1a. FIG. 1a shows the device structure of a conventional power MOSFET.In an N-channel device of this structure, electrons flow from the n⁺diffused source regions horizontally across the p body region (which iselectrically shorted to the source), through a surface channel. Themagnitude of this electron current is under control of the insulatedgate. Past the p body region, the path of the electrons turns downward,vertically crossing the n⁻ epitaxial drift region and going into the n+substrate drain region, the contact for which is on the bottom side ofthe power MOSFET die. From a MOSFET current control standpoint, the FETchannel length, L in FIG. 1a, is determined by the difference in thelateral extent of the p body diffusion and the n⁺ source diffusion, withvalues of the order of L=1 μm typical for power MOSFETs. It is importantto note that the actual on resistance, R_(on), of the standard powerMOSFET device is substantially higher than the channel resistance(specifically, the channel resistance plus twice the source resistance,as for a symmetrical planar MOSFET), due to the electron current pathpassing vertically through the n⁻ drift layer and the n⁺ substratethickness to reach the drain contact.

Comparison of Die Area Required for Deep-Submicron Planar CurrentSwitching MOSFET to Achieve Given Value of R_(on) to Conventional PowerMOSFET

[0149] The principal advantage of this conventional power MOSFET devicestructure, in addition to its ability to handle comparatively largedrain voltages, is its convenient contact arrangement. The high-currentdrain contact covers the entire bottom of the die, while thehigh-current source contact covers most of the top of the die, sharingthat surface with a smaller gate contact. This convenient die contactarrangement makes it easy to package the chip in a simple high currentpackage. The principal disadvantage of the conventional power MOSFETstructure is that even though the structure of source islands withchannel borders shown in FIG. 1a is packed into a dense 2-dimensionalarray covering the die surface, even with an aggressive 10⁶ islands/cm²(10,000/mm²) array packing density, the potential amount of MOSFETperiphery (width, W, of the surface channel per unit area, assuming W=20μm/island), is only about W/A_(chip)=200 mm/mm² (reduced by ˜10% forgate contact area). As a comparison, the planar horizontal geometrycurrent switching MOSFET structure according to aspects of thisinvention gives W/A_(chip)=926 mm/mm² in a nominal 2λ=0.24 μm featuresize CMOS process (or about W/A_(chip)=850 mm/mm² including gate routingarea), 4.63 times higher. Since for a given channel sheet conductance,the channel resistance is proportional to L/W, the other criticaldimension for the power MOSFET is the channel length, L. As noted inFIG. 1a, L=1.0 μm is typical for the channel length of a conventionalpower MOSFET. In comparison, the effective channel length in a 2λ=0.24μm feature size CMOS process is typically L_(eff)=0.19 μm or less. Hencefor the same MOSFET periphery, the deep-submicron short-channel planarMOSFET devices used in aspects of this invention offer nominally 5.26times lower channel resistance than a conventional power MOSFET. Whenthis is combined with the fact that the periphery available in a givenchip area is also 4.63 times higher, for a given chip size, the 2λ=0.24μm feature size CMOS process planar current switching MOSFETs of aspectsof this invention will have a channel resistance over 24 times less thanthat of a conventional power MOSFET.

[0150] The structure of the horizontal or planar geometry short channelcurrent switching MOSFET is illustrated in FIG. 1b. The basic devicestructure consists of a series of parallel n⁺ stripes with poly silicidecontacts, which represent the alternating source and drain electrodes,separated by poly silicide gate electrodes insulated from the siliconsurface by a very thin (e.g., t_(ox)=5.8 nanometers) insulating layerwhich allows channel conduction to be controlled fully with very smallgate voltage changes (ΔV_(gs)˜2.5V). The electron path is essentiallyhorizontal through the surface channel from the n⁺ source to the n⁺drain electrodes. Typical dimensions in a 2λ=0.24 μm feature size CMOSprocess are a nominal gate length of 2λ=0.24 μm (L_(eff)=0.19 mmeffective channel length), with source and drain contact widths of7λ=0.84 μm, for a total MOSFET pitch of 9λ=1.08 μm (the reciprocal ofwhich gives the W/A_(chip)=926 mm/mm² periphery to area ratio citedabove). In fact, it is possible to fabricate substantially higherdensity MOSFETs in a such a λ=0.12 μm CMOS process, with as low as˜6λ=0.72 μm pitch, but in aspects of this invention it is desired tokeep the total device resistance, including contacts and metalinterconnects, as small as possible. Because the sheet resistance of thepoly silicide source and drain contacts is relatively high (˜4Ω/square), it is important to minimize the distance the current passeslaterally through the poly silicide contact before it reaches metal. Asshown in FIG. 1b, a 7λ=0.84 μm source/drain (S/D) stripe width allowsfor a continuous chain of poly silicide to M1 (first level interconnectmetal) via contacts to be placed down the center of these S/D stripes,making the poly silicide degradation of R_(on) negligible.

Comparison of Gate Drive Power Required for Planar Current SwitchingMOSFET to Achieve Given Value of R_(on) to that of Conventional PowerMOSFET

[0151] To reiterate, the enormous (24× nominal) advantage in requiredsilicon die area to achieve a given on resistance of the planar orhorizontal geometry current switching MOSFET structure of aspects ofthis invention as compared to a conventional vertical power MOSFETstructure comes about through the combination of the 4.63× greater FETperiphery, W, that can be packed into a given area (due to the smallerfeature size), and the 5.26× lower channel resistance for a givenperiphery (due to the shorter L_(eff)). This greatly reduced die sizeoffers both a greatly reduced die cost and the opportunity forminiaturizing power conversion products. An additional benefit of thisapproach is the enormous reduction in gate drive power it affords.Ignoring parasitic contributions to gate capacitance, the charge, Q_(g),furnished to the gate electrode will nominally equal the charge inducedin the surface channel of the MOSFET. For an n-channel MOSFET withchannel length, L, having a channel electron mobility of μ_(e), thechannel resistance, R_(ch), at low drain voltages will be given as

R _(ch) =L ²/(μ_(e) Q _(g)) (for very low V _(ds))   Eq. 4

[0152] Comparing the L=1.0 μm channel length of conventional verticalpower MOSFETs with the L_(eff)=0.19 μm channel length of the planardevices of aspects of this invention means that, for the same μ_(e), thegate charge to reach a given R_(ch) value will be 27.7 times smaller forthe new planar current switching MOSFETs. Further, with a gate voltageswing, ΔV_(gs), the ac gate drive power, P_(gd), required to furnishthis gate charge (i.e., to charge and discharge the gate capacitance ,C_(gs)+C_(gd)) at a switching frequency, F_(c), will be given by

P _(gd)=½(C _(gs) +C _(gd))ΔV _(gs) ² F _(c)=½Q _(g) ΔV _(gs) F _(c)  Eq. 5

[0153] The magnitude of the gate voltage swing, ΔV_(gs), required totransfer the gate charge, Q_(g),=(C_(gs)+C_(gd))ΔV_(gs) is determined bythe gate oxide thickness, t_(ox). The gate capacitance of a MOSFET withchannel length, L, and periphery, W, is given by

C _(gs) +C _(gd) =ε _(o)ε_(r) L W/t _(ox)   Eq. 6

[0154] where ε_(o)=8.85×10⁻¹⁴ F/cm and ε_(r)=3.9 for an SiO₂ gatedielectric. From Eqs. 4-6, the channel resistance of the MOSFET will begiven by

R _(ch) =L ²/(μ_(e) Q _(g))=L t _(ox)/(μ_(e) ε _(o) ε _(r) W ΔV _(gs))  Eq. 7

[0155] This means that the gate voltage above threshold, ΔV_(gs),required to reduce the channel resistance to a given R_(ch) value, asgiven by

ΔV _(gs) =L t _(ox)/(μ_(e) ε _(o) ε _(r) W R _(ch))   Eq. 8

[0156] is proportional to the oxide thickness, t_(ox). Substituting Eq.8 into Eq. 5 shows that the amount of ac gate drive power, P_(gd),required to switch the MOSFET to a channel resistance, R_(ch), will begiven by

P _(gd)=½F _(c) L ³ t _(ox)/(μ_(e) ² R _(ch) ² ε _(o) ε _(r) W)   Eq. 9

[0157] This is an important result which indicates that a givenswitching frequency, F_(c), for MOSFETs with the same W/L ratio andchannel mobility, in addition to the factor of L² that comes from therequired gate charge (Eq. 5), the gate drive power expression has anadditional factor of t_(ox) in it. Hence, if we compare the planargeometry current switching MOSFET of aspects of this invention withL_(eff)=0.19 μm and t_(ox)=5.8 nm with a typical vertical geometry powerMOSFET having L=1.0 μm and t_(ox)=100 nm, we see that in addition to theL² advantage of 27.7×, we have a t_(ox) advantage of 17.24×, which meansthat the ac gate drive power is reduced by an factor of 478× by goingfrom a conventional vertical power MOSFET to the deep-submicron planarMOSFET structure of aspects of this invention. This amazing (nearly500×) reduction in gate drive power lets this new planar short channelcurrent switching MOSFET be operated at much higher switching rateswithout seriously compromising power efficiency, which in turn allowsfor greatly reducing the size of switching power converters, etc.,because of the reduced sizes of the capacitors and magnetic elements.

[0158] It should be noted that while Eq. 5 is exact, due to highervertical electric fields at the gate oxide interface, the channelmobilities, μ_(e), in deep-submicron MOSFETs will be somewhat smallerthan those for power MOSFETs. On the other hand, while the total MOSFETdevice “on” resistance, R_(on(f)), of the planar geometry MOSFETs ofaspects of this invention (FIG. 1b) are given from the channelresistance, R_(ch), and the source and drain contact resistances, R_(s)and R_(d), (normally R_(s)≅R_(d) due to symmetry) by

R _(on)(f)=R _(ch) +R _(s) +R _(d) ≅R _(ch)+2R _(s)(for planar MOSFETs)  Eq. 10

[0159] for the unsymmetrical vertical geometry power MOSFET structure ofFIG. 1a, there is a substantial additional drain resistance componentdue to the n⁻ drift layer in FIG. 1a that makes R_(on(f)) substantiallygreater than R_(ch)+2 R_(s). Hence a substantially lower R_(ch) valuemust be achieved in the vertical power MOSFET in order to achieve thesame total device resistance, R_(on(f)),. Additionally, while Eq. 6 is agood approximation for the gate capacitance in the planar MOSFETstructure, the large gate area over the n⁻ drain region (see FIG. 1a)makes the actual gate capacitance at low V_(ds) for the conventionalvertical power MOSFET structure much larger than indicated by Eq. 6.Hence the nearly 500× gate drive power advantage of the planar geometryshort channel MOSFETs of aspects of this invention over conventionalvertical power MOSFETs should at least be reasonably accurate, andprobably understates the advantage.

Capability of Some Embodiments of Invention to Realize Very High-SpeedUltra-Low Q_(d) Body Diode

[0160] The capability of a CMOS integrated circuit fabrication processto make, in addition to the n-channel MOSFETs discussed above, isolatedp-channel MOSFETs (as shown in FIG. 1b), can also be exploited toadvantage in designing high current switching planar MOSFETs as well.FIG. 2a shows the equivalent circuit of a conventional vertical powerMOSFET. Note that, in parallel to the n-channel MOSFET device, there isa robust p-n junction body diode which is capable of passing high levelsof current if the drain is made more negative than the source byV_(fp-n)=1.0 V or so. While in some switching circuit applications wherethe synchronous rectifier switch timing is not precisely matched to thesecondary current timing, the “freewheeling” currents can be handled bythe p-n body diode. Unfortunately, the relatively high forward voltagedrop of the body diode will degrade the power efficiency of low voltageconverters substantially if the duration of the freewheeling currents isa significant fraction of the total switching cycle. In addition to thehigh p-n body diode forward voltage drop, they also have serious chargestorage problems (large Q_(d) values) that limit usable switchingfrequencies. In the short-channel CMOS-implemented planar currentswitching MOSFET device of aspects of this invention, it is possible touse the p-channel device to implement a relatively low forward voltagedrop “diode” having virtually no charge storage (near-zero Q_(d)). Theoptional circuit for adding this “body diode” capability to an n-channeldevice is illustrate in the equivalent circuit of FIG. 2b. This “bodydiode” function is emulated by an active diode-connected p-channelMOSFET (i.e., the gate is connected to the drain). When the drainelectrode becomes more negative than the source by a voltage equal tothe gate threshold voltage, V_(tp), the p-channel device will beginstrong conduction. Since a typical value for this gate threshold voltageis V_(tp)=−0.28V, the V_(fpch) forward conduction voltage drop can bemuch lower than for a p-n junction body diode. When the drain terminalis more positive than the source, as when the n-channel device isconducting normally, the p-channel device conduction is cut off. Thereis negligible charge storage associated with the transient transition ofthis diode-connected p-channel MOSFET “body diode” from strong “forward”conduction to “reverse bias” cutoff (principally the small C_(gs)+C_(gd)of the p-channel MOSFET plus some n-well to p-substrate capacitance).

[0161] As noted in FIG. 2b, this “body diode” function can equally wellbe implemented with an n-channel MOSFET whose gate is connected to itssource. When the drain electrode becomes more negative than the sourceby a voltage equal to the gate threshold voltage, V_(tn), the n-channeldevice will begin strong conduction. This is because when the drain ofthe symmetrical n-channel MOSFET is taken more negative than the source,the source behaves like the drain and visa versa, so the gate is nowconnected to the (effective) drain, which is the usual configuration forconnecting a MOSFET as an active diode. Note that this also means thatif we constrain the gate voltage of the “OFF” large n-channel currentswitching MOSFET to go no more negative than its source[(V_(gs))_(off)=0], then this n-channel current switching MOSFET willact, by itself, as a “body diode” with no additional structuresnecessary.

Interconnect/Packaging Approach for Ultra-Low Resistance Connection ofDeep-Submicron Planar Current Switching MOSFET Die to Circuits

[0162] While the electrical characteristics of the planar geometrydeep-submicron current switching MOSFET structure of aspects of thisinvention represent an enormous improvement over conventional powerMOSFET devices in terms of much smaller die sizes, higher switchingspeeds and remarkably lower gate drive requirements to achieve a givenvalue of on resistance, R_(on), it requires a carefully designedinterconnect and packaging approach to realize the die-level performancein actual circuit application. The basic approach to achieving this isillustrated in FIG. 3, which shows a cross-sectional view of the planar(horizontal) geometry MOSFET structure with its on-chip interconnects,solder ball array die to package mating, and high-current low-resistancepackage. Note that in order to maintain visibility of the on-chipinterconnect structure, the vertical dimensions of the thicker elementssuch as silicon die thickness, die to package (and solder ball)thickness, and thickness of package copper layers have been reduced inFIG. 3.

[0163] The basic interconnect/packaging approach is to make use of anarea array of a large number of source (S) and drain (D) pads, inaddition to a few gate (G) pads, covering the full area of the planargeometry current switching MOSFET die. In a preferred embodiment of thisinvention, illustrated in FIG. 3, solder balls are formed on each ofthese pads for flip-chip mating to the mirror-image pad array on thehigh-current package. As the density of the pad array is increased, orpitch between the solder balls decreased, the height of the solder ballsis generally proportionally decreased. Hence as the center-to-centerpitch, P_(sb), of the solder balls is reduced, the number of balls,N_(sb), on a chip of area, A_(chip),

N _(sb) =A _(chip) /P _(sb) ²   Eq. 11

[0164] increases as 1/P_(sb) ², while the resistance per ball, R_(psb),increases as 1/P_(sb) (since the ball height and diameter go as P_(sb),the height to area ratio goes as P_(sb)/P_(sb) ²=1/P_(sb)), so thecombined solder ball resistance varies as

R _(sb)=4R _(psb) /N _(sb)∝1/P _(sb)   Eq. 12

[0165] (The factor of 4 in Eq. 12 comes from assuming that if there areN_(sb) total solder balls on the die, approximately 50% will be used forsource contacts and the other 50% for drain contacts, accounting for afactor of 2, while the R_(on) will be degraded as the sum of the sourceand drain contributions, accounting for the other factor of 2.) What Eq.12 illustrates is that the total pad contact resistance can be reducedby making the solder ball pitch as small as possible (the ball arraydensity as large as possible). The pitch effect is even stronger in thereduction of the metal spreading resistance, which tends to fall nearlyas 1/N_(sb) or 1/P_(sb) ². Hence the use of a high-density array of asmany solder bumps as possible covering the surface of the die reducesboth the solder bump and the metallization (on-chip and package)contributions to the “on” resistance of the packaged planar currentswitching MOSFET devices. While typical commercial flip-chip solder bumparray pitches of P_(sb)=250 μm are adequate for useful performance, thetotal metallization plus ball resistance can be several times theintrinsic MOSFET device resistance (Eq. 10) (or somewhat less if acopper interconnect metallization technology is used on the chip). Byusing the highest commercially available solder bump array density,P_(sb)=100 μm, the total (chip plus package) metallization plus solderball resistance may be reduced by about a factor of three, to make itcomparable with the intrinsic MOSFET device resistance (e.g. ˜75 μΩ fora 4 mm×4 mm die with a typical aluminum metallization technology).

On-Chip Interconnects

[0166] In the cross-section drawing of FIG. 3, there are 5 levels ofon-chip metallization illustrated, typical for a current 2λ=0.24 μmfeature size commercial CMOS IC foundry process. In the cross sectiondrawing of FIG. 3, and in the associated mask layer sequence layoutdrawings in FIGS. 4A-4B and 5A-5B, the use of the various chipmetallization layers is shown. The chip layout actually begins with theshallow trench isolation of the p-well in which the n-channel MOSFETsare defined. While the shallow trench isolation is not illustrated inFIGS. 4A-4B, it would occupy the 3 μm space between the 25 μm high rowsof MOSFET channels, somewhat wider than the M1 and M2 gate (G) busses.The upper left layout (FIG. 4A) shows the 7λ=0.84 μm wide by 25 μm longpoly silicide source/drain (S/D) stripes, plus the row of 2λ=0.24 μmsquare via cuts which connect them to the M1 stripes above them. TheseM1 stripes, plus their vias up to M2 are shown at the upper right (FIG.4B). The structure up through M1 is also illustrated in the crosssections of FIGS. 1b and 3. As seen at the lower left (FIG. 4C), M2 isdedicated mainly to horizontal S and D busses, plus the smallerhorizontal gate bus (which is in parallel to its counterpart on M1 ).M3, as seen at the lower right (FIG. 4D) (and reproduced at the upperleft FIG. 5A) is a dedicated S (source) plane, with a substantial numberof drain (D) feedthrus (and a much smaller number of gate (G) feedthrus)penetrating it. Similarly, as seen at the upper right in FIG. 5B, M4 isa dedicated D plane, with S and G feedthru patches to reach up to the Sand D contact “checkerboard” (and gate contact “grid” in between) thatmakes up M5. The lower left drawing in FIG. 5C shows a portion a sourceand a drain contact pad and the vertical M5 gate “grid” stripe betweenthem (these tie all of the horizontal M1/M2 G busses together into asingle gate connection, to which are assigned four M5 gate pads). Thetotal chip layout at the lower right illustrates a 4 mm×4 mm chipcarrying 256 solder ball pads on a P_(sb)=250 μm pitch. As illustratedin the cross-sectional drawing of FIG. 3, the actual solder ball base isa 125 μm diameter circle, centered on each of the square M5 contactpads, that is defined by a hole in the oxide protection coating(“scratch mask”).

Package Interconnects

[0167] Because of the concentration of current, and requirement forcarrying the current laterally over substantial (many mm) distances, themetallization thicknesses in the package must be quite substantial(e.g., hundreds of microns of copper in the thicker layers). FIG. 6A andFIG. 6B show respective cross-sectional and plan views of an example ofthe layout of a package with planar bottom source and drain contacts(e.g., suitable for surface mounting on a circuit board). In the exampleillustrated, the base substrate is a 500 μm (20 mil) thickcopper-invar-copper (to provide a coefficient of thermal expansion [CTE]reasonably closely matched to that of the silicon die). While initiallythis base substrate is continuous, during processing it is sawn oretched through for electrical isolation, with the major area chosen asthe source (S) package contact, while a smaller end region (the rightend in FIGS. 6A and 6B) is the drain (D) package contact. The lateralcurrent flow from the drain solder balls from the die to the draincontact end is through a thick copper layer (e.g., 250 mm [20 mils]thick plated copper in FIG. 6B). The lateral current from the sourcesolder balls to the opposite, source contact, end of the package isthrough the 20 mil thick copper-invar-copper substrate, but the currentreaches this substrate by passing through the 10 mil thick Cu drainplane via an array of isolated copper “studs” or “plugs” penetrating theplane.

[0168] While it would be advantageous to make the center-to-center pitchof these studs as fine as possible (e.g., the same pitch as the solderbumps on the die would be ideal), due to the 10 mil thickness of thecopper layer through which they pass this is impractically difficult. Intypical circuit plating processes, the aspect ratio (metal layerthickness divided by minimum horizontal feature size) is typically keptto 1:1 or less. (Higher aspect ratios can be fabricated using moreexotic processes, but their higher costs would make them economicallyunsuitable for most applications at present.) In the package structureillustrated in FIGS. 6A and 6B, the smallest feature to be defined inthe 10 mil thick plated copper layer would be the narrow isolating gap(“moat”) surrounding each source plug (via) penetrating the layer. Theplug itself is of reasonable dimension to carry S current verticallywith low resistance, while the outer rims of the isolation moats do notget too close together or they will impede the lateral flow of draincurrent through this 10 mil thick plated copper drain plane. Hence,keeping the aspect ratio near 1:1, with a 10 mil thick drain plane, thenearest center-to-center stud pitch (diagonal in FIG. 6A) cannot be muchless than 25-30 mils. It is advantageous in the layout to make thehorizontal stud (via plug) pitch an even integer multiple of the diesolder ball pitch, so for the P_(sb)=250 μm (˜10 mil) ball pitch, a1.000 mm (˜40 mil) horizontal stud pitch (0.7071 mm [27.84 mils] minimum[diagonal] pitch) is chosen in FIG. 6A.

[0169] While the drain plane lies directly under the drain solder balls(unless the via stud isolating moats are too large, causing some of thedrain solder ball contacts to fall “off the edge” of the drain planemetal onto the moat), this is not the case for the source solder ballcontacts, only a small fraction of which fall on studs. The connectionof the source solder balls to the studs (via plugs) utilizes anadditional layer or two of copper that is capable of being more finelypatterned than the drain plane (and which hence are much thinner). Thissource plane metallization (seen more easily in the cross-section ofFIG. 3 than in that of FIG. 6B) could have one or two layers of finelinecopper about 10 μm in thickness (about {fraction (1/25)}^(th) of thethickness of the 10 mil thick drain plane). Creating these higherdensity (smaller feature size) multi-layer interconnects requires areasonably flat surface to start with, which means that the moats arefilled around the plugs with a suitable dielectric material andplanarize the dielectric and copper surface before the copper/BCB (orother suitable multilayer dielectric material) interconnect layer(s) areapplied. While the moat diameter shown in FIG. 6A would allow draincontacting and the source plane to be created in one metal layer, inmost cases it would be advantageous to have at least two fineline copperinterconnect layers, both to facilitate getting the drain solder ballcontacts down to the 10 mil copper drain plane and to reduce thespreading resistance from the source studs out to the majority of thesource solder balls that do not sit on studs, as well as to facilitatemaking contact to the gate pads without significantly degrading thissource plane resistance.

Alternative Wafer-Level Additive Copper/Polymer Packaging Approach

[0170] As described in the following section (Table 1), the contributionof metal resistance, both on-chip and package, to R_(on) can be reducedby increasing the density of solder ball contacts between the die andthe package. In the packaging approach illustrated in FIGS. 3 and 6A and6B, the solder balls (“bumps”) are fabricated directly on the completedIC wafer using standard commercial bumping processes (it is alsopossible to bump individual die, but wafer bumping is cheaper). While100 μm solder bump pitches in area arrays are commercially available,the technology is not as well developed as the more common 250 μm pitch,and the reliability is problematical where significant package tosilicon wafer CTE differences may exist. Also, with a 100 μm bump pitch,the need for one or two layers of “fineline” additive interconnect metal(as illustrated in FIGS. 3 and 6A and 6B) to the high-current packagestructure is desired in some aspects. This adds to package complexityand makes finding suitable commercial sources for the package moredifficult.

[0171] The alternative packaging approach illustrated in FIG. 7 achievesthe very low R_(on) of the loom solder ball approach (or exceeds itsperformance) while reducing the demands on both the solder bump matingtechnology and the package. The concept is to fabricate the one or two(as illustrated in FIG. 7) “fineline” metal layers (e.g., 5 μm to 20 μmof copper) with polymer (e.g., BCB or polyimide) interlayer dielectricdirectly on the completed IC wafer in a full-wafer process. Applying theadditive copper/polymer interconnects directly to the “completed” ICwafer (i.e., the wafer has passed through all of the normal fabricationsteps of the CMOS IC foundry) will in general be less expensive and morepractical than adding them on the package side. It is more practicalbecause this copper/polymer technology is not generally available atpackage vendors. It is less expensive because of the fact that die areais smaller than that of the package; hence a smaller area of material issubjected to the cost of the copper/polymer processing when it is placeddirectly on the die. (In the case of very low yields of “good” die onthe IC wafers, the cost of putting the “fineline” copper/polymerinterconnects directly on the IC wafers could exceed that of applyingthem to the packages, but such low yields of good die would not beexpected for mature CMOS foundry processes.)

[0172] In addition to being more practical and lower cost, applying theadditive copper/polymer interconnects directly to the “completed” ICwafer offers the advantage that the density of interconnections betweenthe normal CMOS on-chip metallization and the much thicker “fineline”copper layers is not limited by any solder bump or other joiningtechnology, but only by the via density and metal linewidths availablein the first layer of copper/polymer interconnects. The interconnectdensities practical between the IC chips and an additive copper/polymerare not only much higher than solder bump densities, but there is noreliability penalty associated with going to very high via densities ona chip like there is in joining technologies such as solder bumps. Inthe approach of FIG. 7, there is very little R_(on) penalty associatedwith using relatively coarse solder bump (or solder stripe, etc.)pitches because the of the low sheet resistance of the additive copperlayers. Hence, the solder contacts may go directly from the die (withthe copper/polymer “fineline” layers on it) to very thick metal packagestructures having very coarse feature sizes (such as going to aninterdigitated thick (e.g., >20 mils) copper-invar-copper package orsome form of laminate package).

Alternative Vertical Laminate Package Approach

[0173] The package geometries illustrated in FIGS. 3 and 6A and 6B arehorizontal, in that layers of metal conductors' carrying the high MOSFETsource and drain currents lay parallel to the surface of the MOSFET die.In this geometry, via structures carry current between the differentpatterned layers of package metallization. These vias (morespecifically, the spreading resistance of getting currents into and outof the inter-layer via areas) represent a significant contribution tothe overall package metal resistance, as well as a source of concern forpackage reliability. Also, the fact that the vertical thickness of themetal layers is limited by practical fabrication considerations thatlimit the layer thicknesses to be of the order of the horizontal featuresizes provides a further limitation on package resistance for thehorizontal package geometry.

[0174] These limitations can be overcome and extremely low packageresistances achieved by going to a vertical laminate package geometry,as illustrated for the case of the monolithically-integrated gate driveamplifier (FIG. 8) in FIG. 9A and 9B. In this structure, the high sourceand drain currents are carried in vertical metal layers (that is,perpendicular to the surface of the current switch MOSFET die). Their(horizontal) thickness is limited by the feature size of the diecontacts (e.g., solder bump pitch), but their vertical extent isunlimited, so that extremely low package metal resistance levels can beachieved. Note that ordinarily, the separation of the high current pathsis achieved in the vertical laminate package by sweeping, for example,the layers contacting the source rows of solder balls in one directionand those contacting the drain layers in the opposite direction (e.g.,in the illustration at the bottom (FIG. 9B), the source layers might beswept in the direction into the page, and the drain layers out of thepage). Alternatively, rows may be dedicated to other purposes such aslow inductance V_(dd) connections and they can be taken out of thepackage bottom, in addition to the opposing sides (or either the sourceor drain connection could be taken out of the package bottom ifdesired). Note that while the attachment of this vertical laminatepackage directly to solder balls on die metallization pads is shown inFIG. 9B, this package configuration can also be very advantageously usedwith a die with the additive “fineline” thick copper interconnects addedas illustrated in FIG. 7. When the additional copper/polymerinterconnect layers are added to the die, the pitch of the soldercontacts to the package may be greatly increased without significantlydegrading R_(on). This means that fewer layers of laminate are neededfor the package, making it easier to match the laminate layer pitch tothe solder contact pitch, and potentially making practical the use ofmaterials like copper-invar-copper (CIC) for the metal layers in thelaminate stack for improved CTE match to the silicon die, which wouldoffer the potential for improved reliability. Note that while the use ofCIC in the laminate package stack would alleviate CTE mismatch in theplane of the metal layers, there could still be CTE mismatch in theperpendicular direction due to the CTE of the organic dielectric layersin the stack. If, however, the organic dielectric interlayers are pulledback from the solder interface to the die (further than the pullbackillustrated at the bottom FIG. 9B), then this perpendicular CTE mismatchmay be compensated for by a small amount of bending in the laminatemetal layers.

Calculated Performance for Packaged Planar Current Switching MOSFETDevices

[0175] It is of value to calculate the intrinsic device, on-chip metal,and package metal contributions to the on resistance, R_(on), as well asother critical performance parameters that would be expected for aplanar current switching MOSFET device of the type described in aspectsof this invention. Since, as noted in Eq. 12, the metal interconnectresistance decreases as the density of the solder ball interconnects isincreased, two cases will be presented; one assuming 125 μm balls on a250 μm pitch (standard commercial area array solder ball practice), andthe other assuming 50 μm balls on a 100 μm pitch (highest area arraysolder ball density that is commercially available at present). Asilicon die area of 4 mm×4 mm was assumed for the planar currentswitching MOSFET device, so that the total number of solder balls was256 for the 250 μm pitch or 1600 for the 100 μm pitch case. Using designrules for a commercial 2λ=0.24 μm/L_(eff)=0.1 μm CMOS process, with alayout of the type illustrated in FIGS. 3-5D, a total FET width of 13.5meters is achievable in the 4 mm×4 mm chip size. This process has at_(ox)=5.8 nm gate oxide thickness which gives an N-channel resistance,R_(ch) (Eq. 7), at V_(gs)=+2.5V of 43 μΩ for the L_(eff)=0.19 mm/W=13.5mMOSFET of only 43 μΩ. When the R_(s)=R_(d)=14.1 μΩ source and drainresistances are added to R_(ch) (as per Eq. 10), the intrinsic device onresistance is calculated to be only (R_(on))_(dev)=71.1 mW.

[0176] The CMOS process analyzed has a 5-layer aluminum on-chipmetallization system, with metal layers M1-M4 having a resistance of0.08 Ω/sq and M5 having 0.044 Ω/sq, while the S/D silicide has 4.0Ω/square. The via cut resistances are 7.5 Ω/cut between the S/D silicideand M1, and 5 Ω/cut between M1 and M2 or between other metal layers.While a 7.5 Ω/cut S/D silicide to M1 metal layer resistance may soundserious, for a W=13.5 meter MOSFET width, there are 13.5 million ofthese via cuts in parallel in both the source and drain paths to sharethe current, so the addition to R_(on) is only 1.11 μΩ. This parallelismapplies to the other metal resistance contributions, as a consequence ofa chip interconnect layout (FIGS. 4 and 5) that is well thought out tominimize metal resistance. A resistance build-up analysis of the variousspreading resistances in the on-chip metal planes and the inter-layervia cut resistances gives a calculated on-chip metal resistance of 54.6μΩ in the source lead and 55.9 μΩ in the drain lead (110.5 μΩ total S+D)for the 250 μm solder bump pitch, which drops to 14.1 μΩ in the sourcelead and 15.5 μΩ in the drain lead (29.6 μΩ total S+D) for the finer 100μm solder bump pitch.

[0177] Similarly, the package metal resistance is also a function,though slightly less dramatic, of the solder bump pitch in the flip-chiparea array interconnects between the planar current switching MOSFET dieand its package. A resistance build-up analysis of the various spreadingresistances in the package metal planes and through-layer “plug”resistances gives a calculated package metal resistance of 54.6 μΩ inthe source path and 55.9 μΩ in the drain path (110.5 μΩ total S+D) forthe 250 μm solder bump pitch, which drops to 33.6 μΩ in the source pathand 46.0 μΩ in the drain path (79.7 μΩ total S+D) for the finer 100 μmsolder bump pitch. Table 1 summarizes the contributions to the packageddevice Ron (total source+drain) of the MOSFET device, the on-chipmetallization, and the package metallization (including solder balls)for the “standard” (250 μm) and “high-density” (100 μm) chip-to-packagesolder ball array pitches. TABLE 1 Calculated contributions to R_(on)for planar L_(eff) = 0.19 μm current switching MOSFET (C_(gs) + C_(gd) =20 nF for W = 13.5 m, 4 mm × 4 mm die). Solder Ball Pitch Cases StandardHigh-Density P_(sb) = 250 μm P_(sb) 100 μm Silicon/Transistor (V_(gs) =+2.5 V):  71.1 μΩ  71.1 μΩ On-Chip Metallization: 110.5 μΩ  29.6 μΩPackage Metal: 103.2 μΩ  79.7 μΩ Total Resistance (Si + Metal +Package): 284.8 μΩ 180.4 μΩ

[0178] Note in Table 1 that even with the high-density solder ballpitch, the largest contribution to R_(on) is the metallization, not theMOSFET device itself, and that the largest contribution to the R_(on)resistance is from the package metallization. This is a result of thefact that we have assumed a convenient planar, surface-mountable packageconfiguration (FIGS. 6A and 6B). It would be possible to substantiallyreduce the package metal resistance by reducing the horizontal distancethrough which the source/drain current must pass between the die and thepackage S/D contacts. One package configuration which would accomplishthis would be a vertical package geometry with the source lead on thebottom (as it is under the chip in FIG. 6B), but with the drain lead onthe top, surrounding (and probably covering) the planar MOSFET die. Thiscould be accomplished, for example, by bringing the 10 μm thick platedcopper drain plane up to the surface around the die, and then usingeither a plated copper wall or preform to bring the contact surfaceabove the height of the die. It would be possible to use a cover lid onthis drain contact ring, or leave the back of the die exposed (withsuitable underfill passivation). This configuration would reduce boththe total package area and its contribution to R_(on) substantially, andcould represent a convenient form factor for some applications.

[0179] It should be noted that the flip-chip die underfill noted abovewould probably be utilized in either the flat, surface-mount version ofthe package shown in FIGS. 6A and 6B, or in a vertical package geometryof the type just discussed. One reason for this is that underfill is aneffective means of enhancing solder ball reliability in the face ofdifferential thermal expansion between package and silicon die. Anotheris that the constraint provided by the underfill could be of substantialvalue in reducing lifetime degradation due to electromigration in thesolder bump metal. The planar MOSFET die in this example should be ableto switch currents of 200 amperes, even though the die is only 4 mm×4 mmin size. This pushes, however, the conventional operational currentdensity of solder ball contacts to die for high reliability. This is notviewed as a serious concern, however, both because the constraint of theunderfill should minimize the problem, and because of the way the solderballs are used in this application. In usual flip-chip reliabilityanalyses, it is assumed that the failure of any single solder ballrepresents a functional failure of the part. In this planar currentswitching MOSFET structure, there is massive parallelism between thecurrent-carrying (S/D) solder balls. For example, for the high-density(P_(sb)=100 μm ball pitch) case, there will be a total of 1600 solderballs, or 800 balls in parallel in the source path and 796 balls inparallel in the drain path (assuming 4 balls for gate leads). Thecomplete failure of even 10% or 20% of the solder balls mating the dieto the package would make a barely-perceptible change in the R_(on) ofthe packaged device. (This is because the total S+D solder ballresistance contribution to the 180.4 μΩ R_(on) value is only 8.4 μΩ, andwhile failed balls would also locally increase the metal plane spreadingresistances, the effect of even 20% randomly-distributed ball failuresis very small.) The favorable statistics in this application where 10%to 20% ball failures have no significant effect, as compared to theusual “one ball failure is death” condition allows us to push to higherthan normal current densities in the solder balls. Of course, if solderball electromigration remains an issue in some applications, solder ballmetal compositions more resistant to electromigration effects at thedesired operating temperature can be utilized. Note that as discussed inthe previous section, the alternative packaging approach of fabricatingcopper/polymer “fineline” interconnect layer(s) directly on thecompleted CMOS wafers has the advantage of achieving R_(on) performanceat least as good as shown for 100 μm solder balls in Table 1, whileusing a relatively coarse feature size joining technology which shouldoffer reliability advantages over fine-pitch solder balls.

[0180] It should be noted that whether the planar package configurationof FIGS. 6A and 6B (R_(on)=180.4 μΩ) or the vertical package geometry(R_(on)=125 to 150 μΩ estimated) is used, the packaged deviceresistances are almost unbelievably small for such a small device (4mm×4 mm die, 12 mm×7 mm planar package, or about 6 mm×8 mm for avertical package with the same die). Even at a 200 amp drain current,R_(on)=150 μΩ represents only a V_(ds)=30 mV voltage drop.

Gate Drive Requirements and Optional Device Features

[0181] A dramatic difference between the horizontal or planar geometrydeep-submicron channel length current switching MOSFET structure ofaspects of this invention and conventional vertical geometry powerMOSFETs is in their gate drive requirements. In the example cited above,the total calculated gate capacitance is only C_(gs)+C_(gd)=20 nF (Eq.6, with ε_(r)=3.90, L=0.24 μm, W=13.5 m and t_(ox)=5.8 nm givesC_(gs)+C_(gd)=19.28 nF). This is far (1 to 2 orders of magnitude) lessthan the gate capacitance of conventional vertical power MOSFETs havinga comparable R_(on) values. (Actually, many conventional power MOSFETsconnected in parallel would be required to reach this Ron level; it isthe total C_(gs)+C_(gd) value for the paralleled power MOSFETs that iscompared to the C_(gs)+C_(gd)=20 nF value of the planar switching MOSFETof aspects of this invention.) Also, while conventional power MOSFETsrequire V_(gs)=10 V or more gate voltages to reach low R_(on), withaspects of this invention the values in Table 1 are reached with only aV_(gs)=2.5 V gate drive voltage. As discussed previously, thecombination of the lower value of C_(gs)+C_(gd) and the lower V_(gs)gate drive voltage requirement drastically lowers the (Eq. 5) P_(gd)=½(C_(gs)+C_(gd))ΔV_(gs) ² F_(c) gate drive power requirements for theplanar short-channel current switching MOSFET of aspects of thisinvention (by nearly a factor of 500 over conventional power MOSFETs).

[0182] One of the implications of this enormous reduction in ac gatedrive power is that it becomes practical to sharply increase theswitching frequency, F_(c), without serious efficiency loss due. Thismakes it possible to reduce the size and weight of the capacitive andmagnetic energy storage devices in a power converter circuit, to allow,for example, very small on-board switching power converters to berealized. For example, an V_(out)=1.2V switching converter having amaximum output current of 200 amperes (240 watts peak output) could befabricated with two of these planar geometry current-switching MOSFETs,which would have, even at a very high F_(c)=1 MHz switching rate a totalgate drive power of only P_(gd)=0.125 watts for the two synchronousrectifier switches, or 0.052% of the peak output power. This means thatit would be quite practical to increase switching frequencies up intothe many tens of megahertz range before gate drive power became aserious efficiency concern, which would allow for remarkableminiaturization of power converters.

[0183] The low gate drive power requirements, along with the fact thatthe planar geometry deep-submicron current switching MOSFET devices areconveniently (and inexpensively) fabricated using a standarddeep-submicron CMOS foundry process, suggests a very attractive option:the inclusion of the gate driver amplifier on the same chip with theswitching MOSFET. With conventional power MOSFETs, furnishing clean(“square-wave”) gate drive voltages is a major problem, even atswitching frequencies of the order of F_(c)=100 KHz. While the planargeometry deep-submicron current switching MOSFET devices have lowC_(gs)+C_(gd)=20 nF gate capacitances and are capable of operationat >10 MHz switching frequencies at low gate drive powers, for clean,efficient square-wave gate voltages the pulsed gate currents will besubstantial. For example, if it is desired to keep the gate voltagerisetimes and falltimes to less than 2.5% of the switching period atF_(c)=10 MHz. the voltage risetimes must be under t_(r)=t_(f)=2.5 ns.With ΔV_(gs)=2.5 V and C_(gs)+C_(gd)=2 nF, the gate drive current willpulse to i_(g)=(C_(gs)+C_(gd))(ΔV_(gs)/t_(r))=±20 ampere levels in eachMOSFET during the rise and fall intervals. The distributedinductance/characteristic impedance of usual on-board interconnectsvirtually precludes furnishing gate drive signals of this quality in apractical multi-package on board environment.

[0184] These gate drive signal limitations of conventional packaging canbe overcome in the case of the planar geometry deep-submicron currentswitching MOSFET devices of aspects of this invention by placing thegate driver amplifier on the same silicon chip as the MOSFET, asillustrated in FIG. 8. The gate driver amplifier would consist of ashort chain of CMOS inverters (e.g., 2 to 4 stages typically; FIG. 8shows a 2-stage gate driver) between the gate input to the package/dieand the actual MOSFET gates. In order to minimize ac gate currentdistribution problems, it would probably prove useful to distribute thelast (largest) stage of the gate amplifier chain in sections around thechip. The sizing of the p- and n-channel MOSFET devices in the CMOSdriver inverters can be estimated from the device characteristics andthe desired gate drive currents. Consider a 2-stage CMOS inverter driverfor the 200 ampere current switching MOSFET example, as shown in FIG. 8.The saturated drain current for the L_(eff)=0.19 μm n-channel MOSFETs inthe 2λ=0.24 μm feature size commercial CMOS foundry process isI_(dss)/W=0.6 ma/μm with an R_(on) W=960 Ωμm “on” resistance. Thep-channel devices are about half as good (half the I_(dss)/W and roughlytwice the R_(on) W), so for balanced current drive the p-channel MOSFETsare scaled about twice as wide as the n-channel devices. Forconvenience, the sizing (width, W) of only the n-channel devices will becited, with the understanding that, as shown in FIG. 8, the matchingp-channel pull-up devices will be twice as wide. For a desired gatedrive current pulse of 20 amperes into the W=13.5 meter, 200 amp currentswitching FET, a second-stage driver MOSFET width of W_(d2)=50 mm(I_(dss)=30 amps) would more than suffice. Its R_(on)=0.0192 Ω onresistance would give an t_(rc)=R_(on)(C_(gs)+C_(gd))=0.384 ns timeconstant with the (C_(gs)+C_(gd))=20 nF gate capacitance, which wouldgive excellent gate voltage settling. The input gate capacitance,C_(in2), of this W_(d2)=50 mm driver output stage would be about 75 pFfor the n-channel device and 150 pf for the (2× wider) p-channel MOSFET,or C_(in2)=225 pF total. To drive this 225 pF capacitance over itsΔV_(gs)=2.5V range in Δt_(r)=1 ns would requireI_(in2)=C_(in2)ΔV_(gs)/Δt_(r)=563 ma gate drive current pulses, whichrequire that the prior first-stage driver have an n-channel MOSFET widthof about W_(d1)=1.0 mm (I_(dss)=600 ma). The input capacitance for thisfirst driver stage will be about 1.5 pF for the n-channel, and 3 pF forthe p-channel MOSFETs, or 4.5 pF total gate input capacitance for thechip. Since a 4.5 pF gate driver input capacitance is very easy to drivewith very fast edge rates with typical Z_(o)=5 Ω characteristicimpedance circuit board interconnects, the two-stage driver is more thanadequate. The inclusion of the on-chip gate driver amplifier allows thegate input of this 200 amp planar current switching MOSFET chip to bedriven with remarkable timing precision with nothing more thanconventional digital logic signals and circuit board interconnects. Froma terminal count standpoint, it adds only two package connections; theV_(dd)=+2.5 Vdc and V_(ss)=ground driver amplifier power inputs. Whileit would be possible, in principle, in some applications to tie theinput stage amplifier V_(ss) power lead to the source lead of thecurrent switching MOSFET, in many cases this could lead to feedbackcoupling problems/potential for oscillations on transitions, so aseparate input stage V_(ss) ground lead is preferred. On the other hand,the high peak gate current spikes into the switching demand a very lowimpedance (particularly inductance) connection between the driver outputstage and the switching MOSFET gate, most easily accomplished if we tiethe driver V_(ss) power lead to the source lead of the current switchingMOSFET. A side benefit to tying the V_(ss) lead of the amplifier driver(output) stage to the source of the switching MOSFET is that itautomatically achieves the “body diode” of FIG. 2B. When the input inFIG. 8 is taken “LOW” (≈V_(ss)) to turn off the current switchingMOSFET, its gate will essentially tied its source through the “ON”W_(d2n)=50 μm driver MOSFET. In this state, as noted in FIG. 2B, theW_(n)=13,500 μm current switching MOSFET will begin to conduct any timeits drain voltage becomes more negative than its source by more than itsgate threshold voltage, V_(tn). While connecting the source of theW_(d2n)=50 μm n-channel driver MOSFET directly to the source of theoutput current switch MOSFET solves the problem for handling the large(≈20 ampere) negative gate current peaks, the equally large positivegate current spikes out of the W_(d2p)=100 μm p-channel driver MOSFETmust also be dealt with. In the gate driver amplifier design in FIG. 8,a large (>20 nF) bypass capacitor is included between V_(dd) and thesource of the current switching MOSFET. In the absence if this bypasscapacitor, the full magnitude of the positive gate current spikes wouldhave to be furnished through the V_(dd)=+2.5V gate driver amplifiersupply, which would require an extremely low ac impedance (particularlyinductance) to the V_(dd) lead in order to avoid “voltage starvation”during positive gate current transients which would compromise theswitching process. The inclusion of the on-chip bypass capacitor as anextremely low inductance source of the charge required to charge thegate capacitance of the large current switching MOSFET makes anultra-low inductance V_(dd) connection to the chip unnecessary. It has,however, some chip area/cost penalty. The increase in chip area due tothe gate driver amplifier itself is minimal, adding a total of onlyW_(d(n+p))=153 mm (W_(d2)=50 mm+W_(d1)=1.0 mm, or 51 mm of n-channelMOSFET width, plus twice that, or W_(d1p)+W_(d2p)=102 mm, of p-channelMOSFET width). Hence, this on-chip gate driver would require only about1.1% of the die area. The capability for dispatching theordinarily-odious gate drive problem at an increase of die cost of only1% to 2% is a remarkable side-benefit of implementing the planar currentswitching MOSFET of aspects of this invention in a standarddeep-submicron CMOS integrated circuit foundry process. The inclusion ofthe >20 nF bypass capacitor is more costly. Assuming the IC process hasno special very high capacitance per unit area (C/A) capability (such asvertical geometry capacitors or ferroelectric dielectrics like many DRAMprocesses have, then the highest available C/A is the gate to channelcapacitance. Implementing, using this gate oxide capacitance, a bypasscapacitor whose capacitance equals the gate capacitance of theW_(n)=13,5000 μm current switching MOSFET requires an area equal toapproximately 20% of that of the W_(n)=13,500 μm current switchingMOSFET. Again, this is a small price to pay for a virtually effortlessway of solving the normally odious gate drive problem in high-speedswitchers.

[0185] The capability for integrating other functionality on thecurrent-switching MOSFET die by including CMOS circuitry of varioustypes is also enabled by the use of a CMOS IC process for fabricatingthe devices. These could include various types of analog or digitalcircuitry that would otherwise require separate IC chips in the variousapplications. One example of this would be the inclusion of the switchercontrol circuitry for a power converter (i.e., the analog circuitry thatcompares the actual V_(out) dc output voltage of the converter to thevoltage setpoint value and generates the various primary switching andsecondary output synchronous rectifier switching timing signals neededfor the operation of the power converter. While this would requireadditional package pins, the value added in reduced parts count andpotential for miniaturization would be substantial. Another example,shown in FIG. 2b, would be the inclusion of the “optional ultra-lowQ_(d) diode” to replace the “body, diode“(FIG. 2a) of a normalvertical-geometry power MOSFET. This “body diode” function is emulatedby an active diode-connected p-channel MOSFET (i.e., the gate isconnected to the drain). This device structure and its applications werediscussed in a previous section. Note that it is possible to includeboth the gate driver amplifier and active diode-connected p-channelMOSFET “body diode” options at the same time (i.e., as additions to thesame planar current switching MOSFET die), as could be otherapplication-specific circuitry. Other applications for the planarcurrent switching MOSFFT devices of aspects of this invention couldbenefit from the addition of specialized circuitry designed to serve theneeds of each particular application.

FIGURE CAPTIONS

[0186]FIG. 1a. [Top] Device structure of a conventional verticalgeometry power MOSFET showing lateral electron path through surfacen-channel transitioning to vertical path down to drain contact.

[0187]FIG. 1b. [Bottom] Device structure of n-channel planar/horizontalgeometry high-current switching MOSFET of aspects of this inventionimplemented in a deep-submicron CMOS IC process, showing very shortlateral electron path for very low R_(on). Also illustrated at right isthe capability to include p-channel MOSFETs on same die.

[0188]FIG. 2a. [Left] Equivalent circuit for conventional verticalgeometry n-channel MOS power FET device, showing body diode. Note thatvery large stored diffusion charge, Q_(d), in body diode severely limitsswitching speeds at which it can be used.

[0189]FIG. 2b. [Right] Equivalent circuit for planar/horizontal geometrypower high-current switching MOSFET of aspects of this invention,including optional ultra-low stored charge diode implemented with anactive diode-connected p-channel MOSFET for use when “body diode”functionality is required.

[0190]FIG. 3. Cross-section drawing of planar deep-submicron currentswitching MOSFET of aspects of this invention including high-current dieand package interconnects from source and drain electrodes. Die featuresare drawn to scale for a 2λ=0.24 μm feature size CMOS process, but somepackage/solder ball dimensions reduced to maintain visibility of diefeatures.

[0191] FIGS. 4A-4B. Plan view of layout example for planardeep-submicron current switching MOSFET of aspects of this inventiondrawn to scale for implementation in a 2λ=0.24 μm feature size CMOSprocess. The source/drain and gate poly silicide layers plus the viacuts (small squares) up to the first level metal (M1) are illustrated atthe upper left. At the upper right, M1, the first level of interconnectmetal, is added, and the via cuts to M2 are shown. At the lower left,M2, the second level of interconnect metal, is added, and the via cutsto M3 are shown. At the lower right, M3, the third level of interconnectmetal, dedicated principally to the source plane, is added, and the viacuts to M4 are shown.

[0192] FIGS. 5A-5B. (Continued from FIG. 4). Plan view of layout examplefor planar deep-submicron current switching MOSFET of aspects of thisinvention drawn to scale for implementation in a 2λ=0.24 μm feature sizeCMOS process. At the upper left, M3 and the via cuts to M4 are shown, asin FIG. 4D. At the upper right, M4, the fourth level of interconnectmetal, dedicated principally to the drain plane, is added, and the viacuts to M5 are shown. At the lower left, M5, the fifth and final levelof interconnect metal, used principally for the source, drain and gatesolder ball pads and gate interconnect lines, is added (the scale doesnot permit showing the “pad mask” dielectric opening that defines thecircular solder ball contact areas). At the lower right, the scale hasbeen changed to show the entire 4 mm×4 mm die, shoving the M5 (topmetal) source, drain and gate solder ball pads with gate interconnectlines running in between them, and the “pad mask” dielectric openingthat defines the circular solder ball contact areas.

[0193]FIGS. 6A and 6B. Plan view [top] and cross-sectional view [bottom]of example of a planar package for the planar deep-submicron currentswitching MOSFET of aspects of this invention. Because the high current(e.g., 200 amp) source and drain leads are coplanar on the packagebottom (as well as the ends of the top surface), it would be suitablefor surface mount applications (with an appropriate gate lead extensionfrom the gate pad on the top surface).

[0194]FIG. 7. Example of including optional two CMOS inverter stage gatedriver amplifier on the same die as a 200 amp planar deep-submicroncurrent switching MOSFET of aspects of this invention. Thedriver-amplifier would be capable of supplying 20 to 30 amp gate pulsesto the W=13,500 mm [(C_(gs)+C_(gd))=20 nF] planar switching MOSFET for1.5 to 2 ns risetimes of the 0 to 2.5V gate voltage, while presentingonly about a 4.5 pF capacitive load at the package gate input andrequiring less than 1.5% to 2% of the die area.

[0195]FIG. 8. Example of a gate driver amplifier.

[0196]FIGS. 9A and 9B. Example plan and side views of a verticallylaminated package.

[0197]FIG. 10. 250 μm Bump Pitch Calculation of 0.9 μm Power SwitchingFET Resistance with On-Chip Metal and Package R.

1. An integrated circuit assembly comprising: a semiconductive substratecomprising a plurality of field effect transistors having electricallycoupled sources and electrically coupled drains comprising regions ofthe substrate adjacent to a surface of the substrate, and wherein theelectrically coupled sources and the electrically coupled drains arecollectively configured to conduct power currents in excess of oneAmpere; and a package having a plurality of source contacts and aplurality of drain contacts configured to couple with the electricallycoupled sources and the electrically coupled drains of thesemiconductive substrate, and wherein the source contacts and the draincontacts are provided adjacent to the surface of the package.
 2. Theassembly of claim 1 wherein the semiconductive substrate furthercomprises a plurality of source contacts and a plurality of draincontacts coupled with respective ones of the sources and the drains ofthe field effect transistors, and wherein the source contacts and thedrain contacts of the package are configured to couple with respectiveones of the source contacts and the drain contracts of the powersemiconductor switching device.
 3. The assembly of claim 1 furthercomprising at least one metallization layer coupled with the substrateand configured to couple at least some of the sources in parallel and atleast some of the drains in parallel.
 4. The assembly of claim 3 whereinthe semiconductive substrate further comprises a horizontal interconnectlayer formed upon and coupled with the at least one metallization layer,and the horizontal interconnect layer defines a plurality of sourcecontacts and a plurality of drain contacts configured to couple withrespective ones of the source contacts and the drain contacts of thepackage.
 5. The assembly of claim 1 wherein the package comprises atleast one horizontal interconnect layer to provide the source contactsand the drain contacts.
 6. The assembly of claim 1 wherein allelectrical connections intermediate the sources and the drains of thesubstrate and the source contacts and the drain contacts of the packagepass through the surface of the substrate.
 7. The assembly of claim 1wherein the package includes one terminal source contact and oneterminal drain contact electrically coupled with respective ones of thesource contacts and the drain contacts of the package and adapted toelectrically couple with devices external of the semiconductor switchingdevice.
 8. The assembly of claim 7 wherein the package provides aplurality of electrical paths intermediate the one terminal sourcecontact and the one terminal drain contact and respective ones of thesource contacts and the drain contacts of the package, and theelectrical paths individually have a resistance less than 1 milliOhm. 9.The assembly of claim 1 wherein the semiconductive substrate comprises aflip chip semiconductive die.
 10. The assembly of claim 1 wherein thesource contacts and the drain contacts of the power semiconductor deviceare arranged in alternating columns, and wherein the package comprises avertical laminate package comprising a plurality of conductive layerscorresponding to respective ones of the columns.
 11. The assembly ofclaim 1 wherein the package comprises at least one horizontalinterconnect layer.
 12. The assembly of claim 11 wherein the at leastone horizontal interconnect layer is spaced from the power semiconductordevice; and further comprising a plurality of electrical interconnectsintermediate the horizontal interconnect layer and the source contactsand the drain contacts of the power semiconductor device.
 13. Theassembly of claim 1 wherein the number of source contacts of the powersemiconductor device is less than the number of sources and the numberof drain contacts of the power semiconductor device is less than thenumber of drains.
 14. The assembly of claim 1 wherein the semiconductivesubstrate comprises a monolithic substrate including the field effecttransistors and auxiliary circuitry.
 15. The assembly of claim 1 whereinthe semiconductive substrate comprises a monolithic substrate includingthe field effect transistors and auxiliary circuitry coupled with theplurality of field effect transistors.
 16. The assembly of claim 1wherein the field effect transistors comprise MOSFET devices.
 17. Anintegrated circuit assembly comprising: a power semiconductor switchingdevice comprising: a semiconductive substrate having a surface; and apower transistor formed using the substrate and having a plurality ofsource contacts and drain contacts adjacent to the surface andconfigured to conduct power currents; and a package having a pluralityof source contacts and a plurality of drain contacts corresponding toand electrically coupled with respective ones of the source contacts andthe drain contacts of the power semiconductor device.
 18. The assemblyof claim 17 wherein the power transistor comprises a plurality of planarfield effect transistors.
 19. The assembly of claim 17 wherein the powertransistor comprises a plurality of planar field effect transistorscoupled in parallel.
 20. The assembly of claim 17 further comprising atleast one metallization layer coupled with the substrate and configuredto couple at least some of the source contacts in parallel and at leastsome of the drain contacts in parallel.
 21. The assembly of claim 20further comprising a horizontal interconnect layer formed upon andcoupled with the at least one metallization layer, and the horizontalinterconnect layer defines the source contacts and the drain contacts ofthe power transistor.
 22. The assembly of claim 17 wherein the packagecomprises at least one horizontal interconnect layer to provide thesource contacts and the drain contacts of the package.
 23. The assemblyof claim 17 wherein all electrical connections intermediate the sourcecontacts and the drain contacts of the substrate and the source contactsand the drain contacts of the package pass through the surface of thesubstrate.
 24. The assembly of claim 17 wherein the power transistor isconfigured to conduct power currents in excess of one Ampere.
 25. Theassembly of claim 17 wherein the package includes one terminal sourcecontact and one terminal drain contact electrically coupled withrespective ones of the source contacts and the drain contacts of thepackage and adapted to electrically couple with devices external of thesemiconductor switching device.
 26. The assembly of claim 25 wherein thepackage provides a plurality of electrical paths intermediate the oneterminal source contact and the one terminal drain contact andrespective ones of the source contacts and the drain contacts of thepackage, and the electrical paths individually have a resistance lessthan 1 milliOhm.
 27. The assembly of claim 17 wherein the semiconductivesubstrate comprises a flip chip semiconductive die.
 28. The assembly ofclaim 17 wherein the source contacts and the drain contacts of the powersemiconductor device are arranged in alternating columns, and whereinthe package comprises a vertical laminate package comprising a pluralityof conductive layers corresponding to respective ones of the columns.29. The assembly of claim 17 wherein the package comprises at least onehorizontal interconnect layer.
 30. The assembly of claim 29 wherein theat least one horizontal interconnect layer is spaced from the powersemiconductor device; and further comprising a plurality of electricalinterconnects intermediate the horizontal interconnect layer and thesource contacts and the drain contacts of the power semiconductordevice.
 31. The assembly of claim 17 wherein the number of sourcecontacts of the power semiconductor device is less than the number ofsources and the number of drain contacts of the power semiconductordevice is less than the number of drains.
 32. The assembly of claim 17wherein the semiconductive substrate comprises a monolithic substrateincluding the field effect transistors and auxiliary circuitry.
 33. Theassembly of claim 17 wherein the semiconductive substrate comprises amonolithic substrate including the field effect transistors andauxiliary circuitry coupled with the plurality of field effecttransistors.
 34. The assembly of claim 17 wherein the power transistorcomprises a plurality of MOSFET devices.
 35. A power semiconductorswitching device packaging method comprising: providing a semiconductivesubstrate having a surface; forming a power transistor having pluralityof source contacts and a plurality of drain contacts using thesemiconductive substrate and adjacent to the surface; providing apackage having a plurality of source contacts and a plurality of draincontacts corresponding to the source contacts and drain contacts of thepower transistor; and coupling the source contacts and the draincontacts of the power transistor with the source contacts and the draincontacts of the package.
 36. The method of claim 35 wherein the formingthe power transistor comprises forming a plurality of planar fieldeffect transistors.
 37. The method of claim 35 wherein the forming thepower transistor comprises forming a plurality of planar field effecttransistors coupled in parallel.
 38. The method of claim 35 furthercomprising forming at least one metallization layer to couple at leastsome of the source contacts of the power transistor in parallel and tocouple at least some of the drain contacts of the power transistor inparallel.
 39. The method of claim 38 wherein the at least onemetallization layer forms the source contacts and the drain contacts ofthe power transistor.
 40. The method of claim 38 further comprisingforming a horizontal interconnect layer upon the at least onemetallization layer to form the source contacts and the drain contactsof the power transistor.
 41. The method of claim 35 wherein theproviding the package comprises providing at least one horizontalinterconnect layer providing the source contacts and the drain contactsof the package.
 42. The method of claim 35 wherein the couplingcomprises coupling the source contacts and the drain contacts of thepower transistor with the source contacts and the drain contacts of thepackage to pass all electrical signals communicated intermediate thepower transistor and the package through the surface of thesemiconductive substrate.
 43. The method of claim 35 wherein the formingcomprises forming the power transistor to conduct power currents inexcess of one Ampere.
 44. The method of claim 35 wherein the providingthe package comprises providing the package having a single sourceterminal contact and a single drain terminal contact.
 45. The method ofclaim 35 wherein the providing the semiconductive substrate comprisesproviding a semiconductive die having a flip chip configuration.
 46. Themethod of claim 35 wherein the forming the power transistor comprisesforming the power transistor having the source contacts and the draincontacts arranged in alternating columns.
 47. The method of claim 46wherein the providing the package comprises providing the package havingthe source contacts and the drain contacts arranged in a plurality ofconductive layers corresponding to the columns.
 48. The method of claim35 wherein the providing the package comprises providing the packagehaving at least one horizontal layer coupled with the source contactsand the drain contacts of the package.
 49. The method of claim 35wherein the providing the semiconductive substrate comprises providing amonolithic semiconductive substrate, and further comprising formingauxiliary circuitry using the monolithic semiconductive substrate. 50.The method of claim 35 wherein the providing the semiconductivesubstrate comprises providing a monolithic semiconductive substrate, andfurther comprising forming auxiliary circuitry coupled with the powertransistor.
 51. The method of claim 35 wherein the forming comprisesforming the power transistor to comprise a plurality of MOSFET devices.52. A power semiconductor switching device packaging method comprising:providing a semiconductive substrate comprising a plurality of planarfield effect transistors coupled in parallel and collectively configuredto conduct currents in excess of one Ampere; providing a package havinga plurality of source contacts and a plurality of drain contacts; andcoupling the source contacts and the drain contacts with the planarfield effect transistors.
 53. The method of claim 52 wherein theproviding the semiconductive substrate comprises providing thesemiconductive substrate comprising the planar field effect transistorshaving a plurality of source contacts and a plurality of drain contactsconfigured to couple with respective ones of the source contacts and thedrain contacts of the package.
 54. The method of claim 52 furthercomprising forming at least one metallization layer upon the surface ofthe semiconductive substrate to couple at, least some of the planarfield effect transistors in parallel.
 55. The method of claim 54 whereinthe forming comprises forming the at least one metallization layer todefine a plurality of source contacts and a plurality of drain contactsconfigured to couple with respective ones of the source contacts and thedrain contacts of the package.
 56. The method of claim 54 furthercomprising forming at least one horizontal interconnect layer upon theat least one metallization layer to form a plurality of source contactsand a plurality of drain contacts to couple with respective ones of thesource contacts and the drain contacts of the package.
 57. The method ofclaim 52 wherein the providing the package comprises providing thepackage including at least one horizontal interconnect layer configuredto provide the source contacts and the drain contacts.
 58. The method ofclaim 52 wherein the providing the package comprises providing thepackage having a single source terminal contact and a single drainterminal contact.
 59. The method of claim 52 wherein the couplingcomprises coupling the source contacts and the drain contacts of thepackage with the field effect transistors to pass all electrical signalscommunicated intermediate the field effect transistors and the packagethrough a surface of the semiconductive substrate.
 60. The method ofclaim 52 wherein the providing the semiconductive substrate comprisesproviding a semiconductive die having a flip chip configuration.
 61. Themethod of claim 52 wherein the providing the semiconductive substratecomprises providing the semiconductive substrate having a plurality ofsource contacts and a plurality of drain contacts arranged inalternating columns.
 62. The method of claim 61 wherein the providingthe package comprises providing the package having the source contactsand the drain contacts arranged in a plurality of conductive layerscorresponding to the columns.
 63. The method of claim 52 wherein theproviding the package comprises providing the package having at leastone horizontal layer coupled with the source contacts and the draincontacts of the package.
 64. The method of claim 52 wherein theproviding the semiconductive substrate comprises providing a monolithicsemiconductive substrate having auxiliary circuitry.
 65. The method ofclaim 52 wherein the providing the semiconductive substrate comprisesproviding a monolithic semiconductive substrate having auxiliarycircuitry coupled with the field effect transistors.
 66. The method ofclaim 52 wherein the providing the semiconductive substrate comprisesproviding the semiconductive substrate comprising the planar fieldeffect transistors implemented as MOSFET devices.